Inventor

CLARK LEO JAMES

US50 patents

⚠️ This page may combine multiple inventors who share the name “CLARK LEO JAMES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CLARK LEO JAMES

IBM

Multiprocessor system in which a cache serving as a highest point of coherency is indicated by a snoop response

Optimized cache allocation algorithm for multiple speculative requests

Integrated cache and directory structure for multi-level caches

Software-managed programmable unified/split caching mechanism for instructions and data

Optimizing a cache eviction mechanism by selectively introducing different levels of randomness into a replacement algorithm

Dynamically configurable memory bus and scalability ports via hardware monitored bus utilizations

Layered local cache with lower level cache optimizing allocation mechanism

Mechanism for high performance transfer of speculative request data between levels of cache hierarchy

Time based mechanism for cached speculative data deallocation

Method and system for clearing dependent speculations from a request queue

Layered local cache with lower level cache updating upper and lower level cache directories

Method for upper level cache victim selection management by a lower level cache

Method and system for cancelling speculative cache prefetch requests

Method and apparatus for efficiently managing caches with non-power-of-two congruence classes

Cache allocation policy based on speculative request history

Queue-less and state-less layered local data cache mechanism

Method and system for managing speculative requests in a multi-level memory hierarchy

Layered local cache mechanism with split register load bus and cache load bus

Extended cache state with prefetched stream ID information

Software-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels

Hardware-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels

Victim cache using direct intervention

Victim cache using direct intervention

Method and system for controlling information flow between a producer and a buffer in a high frequency digital system

Data processing system with configurable memory bus and scalability ports

Processor assigning data to hardware partition based on selectable hash of data address

Multiprocessor system with a high performance integrated distributed switch (IDS) controller

L2 cache array topology for large cache with different latency domains

Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer and a shared data path

Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer

Method for providing high availability within a data processing system via a reconfigurable hashed storage subsystem

Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction

Data processing system with fully interconnected system architecture (FISA)

Data processing system having hashed architected processor facilities

Address dependent caching behavior within a data processing system having HSA (hashed storage architecture)

Layered local cache with imprecise reload mechanism

High performance store instruction management via imprecise local cache update mechanism

High performance load instruction management via system bus with explicit register load and/or cache reload protocols

Software-managed programmable congruence class caching mechanism

Hardware-managed programmable congruence class caching mechanism

Communication method for integrated circuit chips on a multi-chip module

L2 cache controller with slice directory and unified cache structure

L2 cache controller with slice directory and unified cache structure

Data processing system with HSA (hashed storage architecture)

Layered speculative request unit with instruction optimized and storage hierarchy optimized partitions

Method for instruction extensions for a tightly coupled speculative request unit

Method and system for controlling information flow between a producer and multiple buffers in a high frequency digital system

L2 cache array topology for large cache with different latency domains

Asymmetrical cache properties within a hashed storage subsystem

CLARK LEO JAMES

Reducing wiring congestion in a cache subsystem utilizing sectored caches with discontiguous addressing