Inventor

STARKE WILLIAM JOHN

US99 patents

⚠️ This page may combine multiple inventors who share the name “STARKE WILLIAM JOHN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STARKE WILLIAM JOHN

IBM

Preprocessing of stored target routines for emulating incompatible instructions on a target processor

System bus structure for large L2 cache array topology with different latency domains

Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line

Method system and apparatus for instruction tracing with out of order processors

Preprocessing of stored target routines for controlling emulation of incompatible instructions on a target processor and utilizing target processor feedback for controlling non-sequential incompatible instruction emulation

Data processing system and method for efficient communication utilizing an Ig coherency state

Cache memory direct intervention

Cross partition sharing of state information

Processor, data processing system and method for synchronizing access to data in shared memory

Processor, data processing system and method for synchronizing access to data in shared memory

Data processing system providing hardware acceleration of input/output (I/O) communication

Cache allocation mechanism for saving multiple elected unworthy members via substitute victimization and imputed worthiness of multiple substitute victim members

Processor virtualization mechanism via an enhanced restoration of hard architected states

Acceleration of input/output (I/O) communication through improved address translation

High speed lock acquisition mechanism with time parameterized cache coherency states

Cache coherency protocol permitting sharing of a locked data granule

Extended cache coherency protocol with a modified store instruction lock release indicator

Extended cache coherency protocol with a “lock released” state

Method and system for clearing dependent speculations from a request queue

Method and system for cancelling speculative cache prefetch requests

Method and system for managing speculative requests in a multi-level memory hierarchy

High performance multiprocessor system with modified-unsolicited cache state

Apparatus and method for executing instructions that select a storage location for output values in response to an operation count

Method and system for instruction trace reconstruction utilizing limited output pins and bus monitoring

Victim cache using direct intervention

Victim cache using direct intervention

Cache directory array recovery mechanism to support special ECC stuck bit matrix

Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism

Recursively accessing a branch target address cache using a target address previously accessed from the branch target address cache

Method and system for controlling information flow between a producer and a buffer in a high frequency digital system

Cache and management method using combined software and hardware congruence class selectors

Partitioned cache and management method for selectively caching data by type

Method and system for initial state determination for instruction trace reconstruction

Method and system for instruction trace reconstruction utilizing performance monitor outputs and bus monitoring

Automatic cache prefetch timing with dynamic trigger migration

Enhanced processor virtualization mechanism via saving and restoring soft processor/system states

Data processing system and method for efficient communication utilizing an Tn and Ten coherency states

Pipelining D states for MRU steerage during MRU/LRU member allocation

L2 cache array topology for large cache with different latency domains

Half-good mode for large L2 cache array topology with different latency domains

System and method of re-ordering store operations within a processor

Cache allocation mechanism for saving elected unworthy member via substitute victimization and imputed worthiness of substitute victim member

Circuits and methods for recovering link stack data upon branch instruction mis-speculation

Method and apparatus for allocating data usages within an embedded dynamic random access memory device

Extended cache coherency protocol with a persistent “lock acquired” state

High performance multiprocessor system with exclusive-deallocate cache state

Cache allocation mechanism for modified-unsolicited cache state that modifies victimization priority bits

Concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers

Method, apparatus, and computer program product in a processor for concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers

ARIMILLI LAKSHMINARAYANA BABA

Processor system and methods of triggering a block move using a system bus write command initiated by user code