Inventor

CHAUDHRY SHAILENDER

US133 patents

⚠️ This page may combine multiple inventors who share the name “CHAUDHRY SHAILENDER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHAUDHRY SHAILENDER

SUN MICROSYSTEMS INC

Method and apparatus for releasing memory locations during transactional execution

Method and apparatus for reporting failure conditions during transactional execution

Circuitry and method for accessing an associative cache with parallel determination of data and data availability

Avoiding locks by transactionally executing critical sections

Selectively monitoring loads to support transactional program execution

Method and apparatus for delaying interfering accesses from other threads during transactional program execution

Method and apparatus for avoiding locks by speculatively executing critical sections

Marking memory elements based upon usage of accessed information during speculative execution

Selectively unmarking load-marked cache lines during transactional program execution

Method and apparatus for supporting different modes of multi-threaded speculative execution

Generation of multiple checkpoints in a processor that supports speculative execution

Patchable and/or programmable pre-decode

Selectively unmarking load-marked cache lines during transactional program execution

Deferring loads and stores when a load buffer or store buffer fills during execute-ahead mode

Method for reducing lock manipulation overhead during access to critical code sections

Method and apparatus for supporting one or more servers on a single semiconductor chip

Selectively deferring instructions issued in program order utilizing a checkpoint and multiple deferral scheme

Automatic prefetch of pointers

Providing fault-tolerance by comparing addresses and data from redundant processors running in lock-step

Method and apparatus for updating an error-correcting code during a partial line store

Supporting inter-process communication through a conditional trap instruction

Method and apparatus for facilitating speculative loads in a multiprocessor system

Method and apparatus for facilitating exception handling using a conditional trap instruction

Method and apparatus for facilitating speculative stores in a multiprocessor system

Monitor entry and exit for a speculative thread during space and time dimensional execution

Parallel join operation to support space and time dimensional program execution

Supporting multi-dimensional space-time computing through object versioning

Dynamic handling of object versions to support space and time dimensional program execution

Method and apparatus for enforcing memory reference dependencies through a load store unit

Method and apparatus for using an assist processor to pre-fetch data values for a primary processor

Supporting space-time dimensional program execution by selectively versioning memory updates

Facilitating garbage collection during object versioning for space and time dimensional computing

Method and apparatus for implementing virtual transactional memory using cache line marking

Arithmetic early bypass

Logging of level-two cache transactions into banks of the level-two cache for system rollback

Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor

Recovering a subordinate strand from a branch misprediction using state information from a primary strand

Efficient store queue architecture

ORACLE AMERICA INC

Method and apparatus for synchronizing threads on a processor that supports transactional memory

Selectively monitoring stores to support transactional program execution

Method and apparatus for tracking load-marks and store-marks on cache lines

Method and apparatus for supporting very large transactions

Starvation-avoiding unbounded transactional memory

Simultaneous speculative threading light mode

Selectively monitoring loads to support transactional program execution

Return address stack recovery in a speculative execution computing apparatus

KARLSSON MARTIN R

Hardware transactional memory acceleration through multiple failure recovery

Precise data return handling in speculative processors

NVIDIA CORP

Memory type which is cacheable yet inaccessible by speculative instructions

CAPRIOLI PAUL

Using address and non-address information for improved index generation for cache memories