Inventor
VERWEGEN PETER
DE5 patents
Patents
5 patentsUS9536030B2Jan 3, 2017
Optimization of integrated circuit physical design
IBM8 citations78
US7560964B2Jul 14, 2009
Latch and clock structures for enabling race-reduced MUX scan and LSSD co-compatibility
IBM7 citations72
US7482851B2Jan 27, 2009
Latch and clock structures for enabling race-reduced mux scan and LSSD co-compatibility
IBM5 citations72
US6147546ANov 14, 2000
Zero volt/zero current fuse arrangement
IBM7 citations70
US7401278B2Jul 15, 2008
Edge-triggered master + LSSD slave binary latch
IBM4 citations59