Inventor

PIAZZA THOMAS A

US61 patents

⚠️ This page may combine multiple inventors who share the name “PIAZZA THOMAS A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PIAZZA THOMAS A

INTEL CORP

Upgrading an integrated graphics subsystem

Method and apparatus for saving power and improving performance in a collapsable pipeline using gated clocks

Method and apparatus for pixel filtering using shared filter resource between overlay and texture mapping engines

Render-cache controller for multithreading, multi-core graphics processor

Method and apparatus for pixel filtering using shared filter resource between overlay and texture mapping engines

Methods and arrangements to interface memory

Memory arbiter with intelligent page gathering logic

Memory arbiter with intelligent page gathering logic

Method and apparatus for effective level of detail selection

3-D rendering texture caching scheme

Methods and systems for rendering line and point features for display

Arbitration mechanism for a computer system having a unified memory architecture

Ordering threads as groups in a multi-threaded, multi-core graphics compute system

Processing architecture having passive threads and active semaphores

Z-buffering techniques for graphics rendering

Memory arbiter with grace and ceiling periods and intelligent page gathering logic

Thread queuing method and apparatus

Behavioral model based multi-threaded architecture

Bandwidth reduction for rendering using vertex data

Bandwidth reduction for zone rendering via split vertex buffers

Hardware based free lists for multi-rate shader

Scatter/gather capable system coherent cache

Recording the results of visibility tests at the input geometry object granularity

Run length encoded digital image

Match MSB digital image compression

Method and apparatus for SIMD structured branching

Position-only shading pipeline

Techniques for efficient GPU triangle list adjacency detection and handling

Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation

Method and apparatus for performing a vertical scale filter function in a graphics device using a single line buffer

Match MSB digital image compression

Hardware stack having entries with a data portion and associated counter

Technique to share information among different cache coherency domains

Technique to share information among different cache coherency domains

Technique to share information among different cache coherency domains

Techniques for efficient GPU triangle list adjacency detection and handling

Dynamically managing memory footprint for tile based rendering

Scatter/gather capable system coherent cache

Technique to share information among different cache coherency domains

REAL 3D INC

Method and apparatus for texture level of detail dithering

Method and apparatus to efficiently interpolate polygon attributes in two dimensions at a prescribed clock rate

Frame buffer memory system for reducing page misses when rendering with color and Z buffers

GEN ELECTRIC

Polygon edge clipping

Spatial augmentation of vertices and continuous level of detail transition for smoothly varying terrain polygon density

JIANG HONG

Visual and graphical data processing using a multi-threaded architecture

Behavioral model based multi-threaded architecture

REAL 3 D

Method and apparatus for effective level of detail selection

OFFEN ZEEV

Technique to share information among different cache coherency domains

PIAZZA THOMAS A

Dynamic allocation of a buffer across multiple clients in a threaded processor

AKENINE-MOLLER TOMAS G

Lossy color merge for multi-sampling anti-aliasing compression