Inventor
YU JIANI
US7 patents
Patents
7 patentsUS8866528B2Oct 21, 2014
Dual flip-flop circuit
NVIDIA CORP7 citations81
US9110141B2Aug 18, 2015
Flip-flop circuit having a reduced hold time requirement for a scan input
NVIDIA CORP4 citations70
US9071240B2Jun 30, 2015
Low power, single-rail level shifters employing power down signal from output power domain and a method of converting a data signal between power domains
NVIDIA CORP2 citations60
US10931266B2Feb 23, 2021
Low power flip-flop element with gated clock
NVIDIA CORP0 citations51
US9842631B2Dec 12, 2017
Mitigating external influences on long signal lines
NVIDIA CORP0 citations51
US8988123B2Mar 24, 2015
Small area low power data retention flop
NVIDIA CORP1 citations51
US10181842B2Jan 15, 2019
Mixed threshold flip-flop element to mitigate hold time penalty due to clock distortion
NVIDIA CORP0 citations38