Inventor

TSAI AARON

US56 patents

⚠️ This page may combine multiple inventors who share the name “TSAI AARON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TSAI AARON

IBM

Method and system for a multi-level virtual/real cache system with synonym resolution

Method and system for handling cache coherency for self-modifying code

Reducing cache transfer overhead in a system

System and method for avoiding deadlocks when performing storage updates in a multi-processor environment

Parallel cache interleave accesses with address-sliced directories

Method, system, and computer program product for handling errors in a cache without processor core recovery

Method, system, and computer program product for cross-invalidation handling in a multi-level private cache

Translation support for a virtual cache

Reducing cache transfer overhead in a system

Cache structure using a logical directory

Reducing cache transfer overhead in a system

Cache structure using a logical directory

Reducing cache transfer overhead in a system

Reducing cache transfer overhead in a system

Cache miss thread balancing

Reducing cache transfer overhead in a system

System and method for simultaneous access of the same line in cache storage

System and method for simultaneous access of the same doubleword in cache storage

Translation support for a virtual cache

Method of implementing a translation lookaside buffer with support for a real space control

Using a shadow copy of a cache in a cache hierarchy

Special tracking pool enhancement for core local cache address invalidates

Cache management

Cache miss thread balancing

Cache management

Cross-core invalidation snapshot management

Shadow pointer directory in an inclusive hierarchical cache

Processor cross-core cache line contention management

Load reissuing using an alternate issue queue

Translation support for a virtual cache

Cache structure using a logical directory

Translation support for a virtual cache

Efficient pointer load and format

Efficient pointer load and format

Efficient pointer load and format

Store data forwarding with no memory model restrictions

Target buffer address region tracking

Instruction to move data in a right-to-left direction

Optimizing grouping of instructions

Optimizing grouping of instructions

TSAI AARON

Vertically assembled compact

Store data forwarding with no memory model restrictions

POWER MATE TECHNOLOGY CO LTD

Heat-dissipating structure of circuit board

Heat-dissipative coating

PRASKY BRIAN R

Cache set selective power up

High performance cache translation look-aside buffer (TLB) lookups using multiple page size prediction

JACOBI CHRISTIAN

Managing cache coherency for self-modifying code in an out-of-order execution system

BOHN RICHARD E

System, method and processor for accessing data after a translation lookaside buffer miss

BONANNO JAMES J

Target buffer address region tracking

BARRICK BRIAN D

Specialized store queue and buffer design for silent store implementation