Inventor

SRIVASTAVA KAMALESH K

US33 patents

⚠️ This page may combine multiple inventors who share the name “SRIVASTAVA KAMALESH K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SRIVASTAVA KAMALESH K

IBM

Method of forming dual height solder interconnections

Solder mass having conductive encapsulating arrangement

Reactive Ion Etching chamber design for flip chip interconnections

Sacrificial seed layer process for forming C4 solder bumps

Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization

Control of gas content in process liquids for improved megasonic cleaning of semiconductor wafers and microelectronics substrates

Low impedance power distribution structure for a semiconductor chip package

Palladium enhanced fluxless soldering and bonding of semiconductor device contacts

Multilayer pillar for reduced stress interconnect and method of making same

Multilayer pillar for reduced stress interconnect and method of making same

Multilayer pillar for reduced stress interconnect and method of making same

Method for selective electroplating of semiconductor device I/O pads using a titanium-tungsten seed layer

Method for forming robust solder interconnect structures by reducing effects of seed layer underetching

I/C chip suitable for wire bonding

Palladium enhanced soldering and bonding of semiconductor device contacts

Multilayer pillar for reduced stress interconnect and method of making same

Multilayer pillar for reduced stress interconnect and method of making same

Method for forming robust solder interconnect structures by reducing effects of seed layer underetching

Process of etching a titanium/tungsten surface and etchant used therein

Flip-chip assembly with organic chip carrier having mushroom-plated solder resist opening

Multilayer pillar for reduced stress interconnect and method of making same

Additives for grain fragmentation in Pb-free Sn-based solder

Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers

Method of forming a bond pad on an I/C chip and resulting structure

Method and process for reducing undercooling in a lead-free tin-rich solder alloy

Method and process for reducing undercooling in a lead-free tin-rich solder alloy

JADHAV VIRENDRA R

Multilayer pillar for reduced stress interconnect and method of making same

Multilayer pillar for reduced stress interconnect and method of making same

Multilayer pillar for reduced stress interconnect and method of making same

ARVIN CHARLES L

Additives for grain fragmentation in Pb-free Sn-based solder

BELANGER LUC

Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers

BUSBY JAMES A

Optimization of metallurgical properties of a solder joint

TESSERA INTELLECTUAL PROPERTIE

Forming robust solder interconnect structures by reducing effects of seed layer underetching