Inventor
KNICKERBOCKER SARAH H
US33 patents
⚠️ This page may combine multiple inventors who share the name “KNICKERBOCKER SARAH H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
28 patentsUS6335210B1Jan 1, 2002
Baseplate for chip burn-in and/of testing, and method thereof
IBM64 citations96
US5541005AJul 30, 1996
Large ceramic article and method of manufacturing
IBM64 citations94
US5283104AFeb 1, 1994
Via paste compositions and use thereof to form conductive vias in circuitized ceramic substrates
IBM80 citations94
US9401336B2Jul 26, 2016
Dual layer stack for contact formation
IBM48 citations93
US6661100B1Dec 9, 2003
Low impedance power distribution structure for a semiconductor chip package
IBM32 citations92
US5139851AAug 18, 1992
Low dielectric composite substrate
IBM22 citations92
US5337475AAug 16, 1994
Process for producing ceramic circuit structures having conductive vias
IBM37 citations91
US5185215AFeb 9, 1993
Zirconia toughening of glass-ceramic materials
IBM26 citations91
US5135595AAug 4, 1992
Process for fabricating a low dielectric composite substrate
IBM24 citations91
US7144490B2Dec 5, 2006
Method for selective electroplating of semiconductor device I/O pads using a titanium-tungsten seed layer
IBM14 citations84
US5277725AJan 11, 1994
Process for fabricating a low dielectric composite substrate
IBM17 citations81
US6995084B2Feb 7, 2006
Method for forming robust solder interconnect structures by reducing effects of seed layer underetching
IBM7 citations74
US5139975AAug 18, 1992
Sintering arrangement for enhancing removal of carbon from ceramic substrate laminates
IBM12 citations74
US5053361AOct 1, 1991
Setter tile for use in sintering of ceramic substrate laminates
IBM10 citations74
US6995475B2Feb 7, 2006
I/C chip suitable for wire bonding
IBM9 citations73
US4971738ANov 20, 1990
Enhanced removal of carbon from ceramic substrate laminates
IBM16 citations73
US7833897B2Nov 16, 2010
Process for making interconnect solder Pb-free bumps free from organo-tin/tin deposits on the wafer surface
IBM7 citations71
US9362223B2Jun 7, 2016
Integrated circuit assembly with cushion polymer layer
IBM4 citations70
US7473997B2Jan 6, 2009
Method for forming robust solder interconnect structures by reducing effects of seed layer underetching
IBM4 citations62
US5167913ADec 1, 1992
Method of forming an adherent layer of metallurgy on a ceramic substrate
IBM6 citations62
US5173331ADec 22, 1992
Zirconia toughening of glass-ceramic materials
IBM5 citations61
US7999377B2Aug 16, 2011
Method and structure for optimizing yield of 3-D chip manufacture
IBM2 citations60
US7737003B2Jun 15, 2010
Method and structure for optimizing yield of 3-D chip manufacture
IBM4 citations60
US8807184B2Aug 19, 2014
Reduction of edge chipping during wafer handling
IBM1 citations52
US7572726B2Aug 11, 2009
Method of forming a bond pad on an I/C chip and resulting structure
IBM0 citations51
US9209128B2Dec 8, 2015
Integrated circuit assembly with cushion polymer layer
IBM0 citations49
US9171749B2Oct 27, 2015
Handler wafer removal facilitated by the addition of an amorphous carbon layer on the handler wafer
IBM0 citations42
US7666780B2Feb 23, 2010
Alignment verification for C4NP solder transfer
IBM0 citations39