Inventor

FUJIOKA SHINYA

JP103 patents

⚠️ This page may combine multiple inventors who share the name “FUJIOKA SHINYA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FUJIOKA SHINYA

FUJITSU LTD

Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations

Semiconductor integrated circuit and method for controlling the same

Step-up circuit using two frequencies

Semiconductor memory for increasing the number of half good memories by selecting and using good memory blocks

Circuit for entering/exiting semiconductor memory device into/from low power consumption mode and method of controlling internal circuit at low power consumption mode

Semiconductor memory device, and method of controlling the same

Semiconductor memory device, and method of controlling the same

Dynamic random access memory having a low power consumption mode, and method of operating the same

Semiconductor memory device having a refresh operation

Semiconductor integrated circuit memory

High-speed random access memory device

Semiconductor memory device

Clock generator having DLL and semiconductor device having clock generator

Semiconductor memory device for masking all bits in a test write operation

Semiconductor device

DRAM for storing data in pairs of cells

Memory device with faster reset operation

Synchronous semiconductor memory device and bus control method

Bit line reset circuit of memory

Semiconductor memory device with row access in selected column block

High-speed clock-synchronous semiconductor integrated circuit and semiconductor integrated circuit system

Semiconductor device with appropriate power consumption

Volatile memory device and method of refreshing same

Memory circuit having parity cell array

Semiconductor memory having burst transfer function and internal refresh function

Semiconductor memory of a dynamic random access memory (DRAM) type having a static random access memory (SRAM) interface

Reduced potential generation circuit operable at low power-supply potential

Semiconductor memory

Fuse circuit

Semiconductor memory device

Semiconductor memory device having an SRAM and a DRAM on a single chip

Semiconductor memory device

Semiconductor memory device with reduced power consumption

Semiconductor memory device

Semiconductor integrated circuit having circuit for writing data to memory cell

Semiconductor memory and burn-in test method of semiconductor memory

Semiconductor memory device and information processing system

Memory device

Semiconductor memory device and memory system

Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless

Semiconductor integrated circuit

Semiconductor memory

Semiconductor memory device

Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless of whether a preceding address and a present address match each other

FUJITSU MICROELECTRONICS LTD

Semiconductor memory device, and method of controlling the same

Memory device

NIIBE MASAO

Passive optical network system

FUJIOKA SHINYA

Memory system and method that changes voltage and frequency

MORI KAORU

Semiconductor device

FUJIHIRA KENJI

Packet transfer system, network management apparatus, and edge node