Inventor

FALTERMEIER JOHNATHAN E

US53 patents

⚠️ This page may combine multiple inventors who share the name “FALTERMEIER JOHNATHAN E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FALTERMEIER JOHNATHAN E

IBM

High-K/metal gate CMOS finFET with improved pFET threshold voltage

STI formation in semiconductor device including SOI and bulk silicon regions

Deep slit isolation with controlled void

Variable stoichiometry silicon nitride barrier films for tunable etch selectivity and enhanced hyrogen permeability

Low-cost deep trench decoupling capacitor device and process of manufacture

Uniform finFET gate height

Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor

Process for fabricating a uniform gate oxide of a vertical transistor

High-K layer chamfering to prevent oxygen ingress in replacement metal gate (RMG) process

Gate structure cut after formation of epitaxial active regions

finFETs containing improved strain benefit and self aligned trench isolation structures

Self-aligned patterned etch stop layers for semiconductor devices

Source/drain junction for high performance MOSFET formed by selective EPI process

DRAM having deep trench capacitors with lightly doped buried plates

Providing isolation for wordline passing over deep trench capacitor

Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask

Gate structure cut after formation of epitaxial active regions

Partially dielectric isolated fin-shaped field effect transistor (FinFET)

Nitridation on HDP oxide before high-k deposition to prevent oxygen ingress

Process for fabricating a uniform gate oxide of a vertical transistor

Quantum conductive recrystallization barrier layers

STI formation for vertical and planar transistors

Replacement metal gate stack for diffusion prevention

Replacement metal gate stack for diffusion prevention

Trench capacitor with void-free conductor fill

Microelectronic element having trench capacitors with different capacitance values

Self-aligned contact

STI formation in semiconductor device including SOI and bulk silicon regions

Doped structures containing diffusion barriers

Dopant control of semiconductor devices

Highly scalable trench capacitor

Replacement metal gate stack for diffusion prevention

Gate structure cut after formation of epitaxial active regions

Partially dielectric isolated fin-shaped field effect transistor (FinFET)

Nitridation on HDP oxide before high-k deposition to prevent oxygen ingress

Semiconductor structure having buried conductive elements

Semiconductor structure having buried conductive elements

Uniform recess of a material in a trench independent of incoming topography

BASKER VEERARAGHAVAN S

High-K/metal gate CMOS finFET with improved pFET threshold voltage

FinFET spacer formation by oriented implantation

Spacer as hard mask scheme for in-situ doping in CMOS finFETs

CHENG KANGGUO

Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (SOI) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor

Smooth and vertical semiconductor fin structure

Highly scalable trench capacitor

GLOBALFOUNDRIES INC

FinFET spacer formation by oriented implantation

FinFET spacer formation by oriented implantation

BEDELL STEPHEN W

Device structure, layout and fabrication method for uniaxially strained transistors

Device structure, layout and fabrication method for uniaxially strained transistors

FALTERMEIER JOHNATHAN E

Stress enhanced transistor devices and methods of making

Stress enhanced transistor devices and methods of making