Inventor

ENDERS GERHARD

DE30 patents

⚠️ This page may combine multiple inventors who share the name “ENDERS GERHARD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ENDERS GERHARD

INFINEON TECHNOLOGIES AG

DRAM memory cell and memory cell array with fast read/write access

DRAM memory having vertically arranged selection transistors

Semiconductor memory with vertical selection transistor

Semiconductor gate structure and method for fabricating a semiconductor gate structure

Method for fabricating a semiconductor memory device

Trench cell for a DRAM cell array

Method for manufacturing a buried strap contact in a memory cell

Method for fabricating a semiconductor memory device

DRAM memory with vertically arranged selection transistors

Dram cell and space-optimized memory array

Static random access memory (SRAM)

Method for fabricating a gate structure of a FET and gate structure of a FET

Vertical transistor, and a method for producing a vertical transistor

Field-effect transistor

Method for fabricating a vertical transistor, and semiconductor memory cell having a trench capacitor and an associated vertical selection transistor

Integrated semiconductor memory with a selection transistor formed at a ridge

FeRAM memory and method for manufacturing it

Method for processing a substrate to form a structure

Buried strap contact for a storage capacitor and method for fabricating it

Method for fabricating a semiconductor memory device

INFINEON TECHNOLOGIES RICHMOND

Double gated transistor

Double gated transistor

SIEMENS AG

Method for forming a high surface area trench capacitor

Method for manufacturing VLSI MOS-transistor circuits

SOITEC SILICON ON INSULATOR

Back gate in select transistor for eDRAM

Sense amplifier with dual gate precharge and decode transistors

INFINEON TECHNOLOGIES CORP

Memory cell having trench capacitor and vertical, dual-gated transistor

FERRANT RICHARD

Semiconductor memory having staggered sense amplifiers associated with a local column decoder

ENDERS GERHARD

Fully depleted SOI device with buried doped layer

MOLL HANS-PETER

Interconnect structure for semiconductor devices