Inventor
KIRIHATA TOSHIAKI K
US12 patents
Patents
12 patentsUS7203794B2Apr 10, 2007
Destructive-read random access memory system buffered with destructive-read memory cache
IBM21 citations92
US6768692B2Jul 27, 2004
Multiple subarray DRAM having a single shared sense amplifier
IBM18 citations92
US6426914B1Jul 30, 2002
Floating wordline using a dynamic row decoder and bitline VDD precharge
IBM37 citations92
US6751151B2Jun 15, 2004
Ultra high-speed DDP-SRAM cache
IBM17 citations84
US6512683B2Jan 28, 2003
System and method for increasing the speed of memories
IBM13 citations84
US6831866B1Dec 14, 2004
Method and apparatus for read bitline clamping for gain cell DRAM devices
IBM14 citations83
US6801980B2Oct 5, 2004
Destructive-read random access memory system buffered with destructive-read memory cache
IBM13 citations83
US7057866B2Jun 6, 2006
System and method for disconnecting a portion of an integrated circuit
IBM8 citations73
US6948028B2Sep 20, 2005
Destructive-read random access memory system buffered with destructive-read memory cache
IBM10 citations73
US6751152B2Jun 15, 2004
Method and configuration to allow a lower wordline boosted voltage operation while increasing a sensing signal with access transistor threshold voltage
IBM12 citations73
US6542973B2Apr 1, 2003
Integrated redundancy architecture system for an embedded DRAM
IBM12 citations73
US6519174B2Feb 11, 2003
Early write DRAM architecture with vertically folded bitlines
IBM10 citations73