Inventor

HAN JIN-MAN

US69 patents

⚠️ This page may combine multiple inventors who share the name “HAN JIN-MAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HAN JIN-MAN

MICRON TECHNOLOGY INC

Architecture and method for NAND flash memory

Memory device trims

Programming memory devices

Programming memory devices

Flash memory programming to reduce program disturb

Method of storing data on a flash memory device

Erase operation control sequencing apparatus, systems, and methods

Memory device having a negatively ramping dynamic pass voltage for reducing read-disturb effect

Wordline voltage transfer apparatus, systems, and methods

NAND system with a data write frequency greater than a command-and-address-load frequency

Non-volatile memory device with both single and multiple level cells

Programming memory devices

Random cache read

Method of storing data on a flash memory device

Flash memory programming to reduce program disturb

Architecture and method for NAND flash memory

Random cache read

Programming memory devices

Method, apparatus, and system providing adjustable memory page configuration

Memory block reallocation in a flash memory device

Memory with interleaved read and redundant columns

NAND system with a data write frequency greater than a command-and-address-load frequency

Flash memory device with redundant columns

SAMSUNG ELECTRONICS CO LTD

Column redundancy circuit for a semiconductor memory device

High speed and low power signal line driver and semiconductor memory device using the same

Nonvolatile memory devices, methods of operating the same and solid state drives including the same

Integrated circuit memory device including banks of memory cells and related methods

Apparatus for automatically initiating a stress mode of a semiconductor memory device

Method and circuit for controlling an isolation gate in a semiconductor memory device

Row address control circuits having a predecoding address sampling pulse generator and methods for memory devices

Circuit for sensing back-bias level in a semiconductor memory device

HAN JIN-MAN

Memory device with a decreasing dynamic pass voltage for reducing read-disturb effect

Method of storing data on a flash memory device

Memory block reallocation in a flash memory device

Method apparatus, and system providing adjustable memory page configuration

Method of storing data on a flash memory device

Non-volatile memory device with both single and multiple level cells

Flash memory device with redundant columns

T RAM INC

Reference cells for TCCT based memory cells

Single data line sensing scheme for TCCT-based memory cells

Memory architecture for TCCT-based memory cells

Reference cells for TCCT based memory cells

Single data line sensing scheme for TCCT-based memory cells

SAMSUNG ELECTRO MECH

Chip resistor element

Chip resistor

T RAM SEMICONDUCTOR INC

Single data line sensing scheme for TCCT-based memory cells

SILICON MAGIC CORP

Method and structure for refresh operation with a low voltage of logic high in a memory device

SHIM SUNIL

Control method of nonvolatile memory device

KIM MIN SEOK

Method of programming nonvolatile memory device

ROUND ROCK RES LLC

Non-volatile memory device with both single and multiple level cells