Inventor
AATRESH DEEPAK J
US7 patents
⚠️ This page may combine multiple inventors who share the name “AATRESH DEEPAK J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
4 patentsUS5586332ADec 17, 1996
Power management for low power processors through the use of auto clock-throttling
INTEL CORP143 citations97
US5469544ANov 21, 1995
Central processing unit address pipelining
INTEL CORP32 citations92
US5398244AMar 14, 1995
Method and apparatus for reduced latency in hold bus cycles
INTEL CORP51 citations92
US5954814ASep 21, 1999
System for using a branch prediction unit to achieve serialization by forcing a branch misprediction to flush a pipeline
INTEL CORP7 citations73