Inventor

CHATURVEDULA KAVITHA

US6 patents

⚠️ This page may combine multiple inventors who share the name “CHATURVEDULA KAVITHA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LSI CORP

4 patents

US7895546B2Feb 22, 2011

Statistical design closure

LSI CORP100 citations95

US7844929B2Nov 30, 2010

Optimizing test code generation for verification environment

LSI CORP4 citations60

US7594201B2Sep 22, 2009

Enhanced method of optimizing multiplex structures and multiplex control structures in RTL code

LSI CORP2 citations59

US8001497B2Aug 16, 2011

Control signal source replication

LSI CORP0 citations49

LSI LOGIC CORP

2 patents

US7082584B2Jul 25, 2006

Automated analysis of RTL code containing ASIC vendor rules

LSI LOGIC CORP40 citations87

US7086015B2Aug 1, 2006

Method of optimizing RTL code for multiplex structures

LSI LOGIC CORP3 citations55