Inventor
STEEGEN AN L
US21 patents
Patents
21 patentsUS6921711B2Jul 26, 2005
Method for forming metal replacement gate of high performance
IBM147 citations99
US6891192B2May 10, 2005
Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions
IBM179 citations99
US6869866B1Mar 22, 2005
Silicide proximity structures for CMOS device performance improvements
IBM53 citations96
US7291528B2Nov 6, 2007
Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions
IBM16 citations92
US7067368B1Jun 27, 2006
Method for forming self-aligned dual salicide in CMOS technologies
IBM17 citations92
US7056782B2Jun 6, 2006
CMOS silicide metal gate integration
IBM25 citations92
US6936522B2Aug 30, 2005
Selective silicon-on-insulator isolation structure and method
IBM37 citations92
US7396714B2Jul 8, 2008
Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions
IBM11 citations84
US6927117B2Aug 9, 2005
Method for integration of silicide contacts and silicide gate metals
IBM15 citations84
US7429752B2Sep 30, 2008
Method and structure for forming strained SI for CMOS devices
IBM4 citations74
US7129126B2Oct 31, 2006
Method and structure for forming strained Si for CMOS devices
IBM9 citations74
US7112481B2Sep 26, 2006
Method for forming self-aligned dual salicide in CMOS technologies
IBM5 citations74
US7411227B2Aug 12, 2008
CMOS silicide metal gate integration
IBM7 citations73
US7326983B2Feb 5, 2008
Selective silicon-on-insulator isolation structure and method
IBM8 citations73
US7928443B2Apr 19, 2011
Method and structure for forming strained SI for CMOS devices
IBM1 citations63
US7550338B2Jun 23, 2009
Method and structure for forming strained SI for CMOS devices
IBM1 citations63
US7064025B1Jun 20, 2006
Method for forming self-aligned dual salicide in CMOS technologies
IBM4 citations63
US7923786B2Apr 12, 2011
Selective silicon-on-insulator isolation structure and method
IBM3 citations62
US7655557B2Feb 2, 2010
CMOS silicide metal gate integration
IBM4 citations62
US7081397B2Jul 25, 2006
Trench sidewall passivation for lateral RIE in a selective silicon-on-insulator process flow
IBM5 citations62
US7700951B2Apr 20, 2010
Method and structure for forming strained Si for CMOS devices
IBM0 citations52