Inventor

SCHARDT PAUL E

US131 patents

⚠️ This page may combine multiple inventors who share the name “SCHARDT PAUL E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCHARDT PAUL E

IBM

Dynamic thread status retrieval using inter-thread communication

Dynamic virtual software pipelining on a network on chip

Network on chip with low latency, high bandwidth application messaging interconnects that abstract hardware inter-thread data communications into an architected state of a processor

Monitoring software pipeline performance on a network on chip

Instruction set architecture with opcode lookup using memory attribute

Selecting and using a cloud-based hardware accelerator

Extensible execution unit interface architecture with multiple decode logic and multiple execution units

Indirect instruction predication

Indirect instruction predication

Extensible execution unit interface architecture with multiple decode logic and multiple execution units

Local instruction loop buffer utilizing execution unit register file

Concurrent multiple instruction issue of non-pipelined instructions using non-pipelined operation resources in another processing core

Dynamic thread status retrieval using inter-thread communication

Dynamic thread status retrieval using inter-thread communication

Instruction set architecture with secure clear instructions for protecting processing unit architected state information

Instruction set architecture with secure clear instructions for protecting processing unit architected state information

Providing performance tuned versions of compiled code to a CPU in a system of heterogeneous cores

Graphics rendering on a network on chip

Implementing system irritator accelerator FPGA unit (AFU) residing behind a coherent attached processors interface (CAPI) unit

Implementing system irritator accelerator FPGA unit (AFU) residing behind a coherent attached processors interface (CAPI) unit

Accelerator validation and reporting

Dynamic thread status retrieval using inter-thread communication

Accelerator management

Instruction set architecture with opcode lookup using memory attribute

Instruction set architecture with opcode lookup using memory attribute

Floating point execution unit for calculating packed sum of absolute differences

Floating point execution unit for calculating packed sum of absolute differences

Extensible execution unit interface architecture with multiple decode logic and multiple execution units

Local instruction loop buffer utilizing execution unit register file

MEJDRICH ERIC O

Performance event triggering through direct interthread communication on a network on chip

Software pipelining on a network on chip

Single step mode in a software pipeline within a highly threaded network on a chip microprocessor

Instruction buffer bypass of target instruction in response to partial flush

Software pipelining on a network on chip

DMA-based acceleration of command push buffer between host and target devices

Parallelized ray tracing

Multithreaded software rendering pipeline with dynamic performance-based reallocation of raster threads

Propagating shared state changes to multiple threads within a multithreaded processing environment

Sequential processing in network on chip nodes by threads generating message containing payload and pointer for nanokernel to access algorithm to be executed on payload in another node

Rolling texture context data structure for maintaining texture data in a multithreaded image processing pipeline

MUFF ADAM J

Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levels

Memory address translation-based data encryption with integrated encryption engine

Memory address translation-based data encryption/compression

Instruction predication using instruction filtering

FOWLER DAVID K

Accelerated data structure optimization based upon view orientation

Physical rendering with textured bounding volume primitive mapping

HOOVER RUSSELL D

Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message data

KUESEL JAMIE R

Indirect inter-thread communication using a shared pool of inboxes

GREENWOOD JASON

Inter-thread communication with software security

GLOBALFOUNDRIES INC

Instruction set architecture with extensible register addressing