Inventor
SHIUE RUEY-YUN
TW13 patents
Patents
13 patentsUS5923088AJul 13, 1999
Bond pad structure for the via plug process
TAIWAN SEMICONDUCTOR MFG96 citations96
US5700735ADec 23, 1997
Method of forming bond pad structure for the via plug process
TAIWAN SEMICONDUCTOR MFG126 citations96
US5946567AAug 31, 1999
Method for making metal capacitors for deep submicrometer processes for semiconductor integrated circuits
TAIWAN SEMICONDUCTOR MFG49 citations95
US9209048B2Dec 8, 2015
Two step molding grinding for packaging applications
TAIWAN SEMICONDUCTOR MFG19 citations92
US6211069B1Apr 3, 2001
Dual damascene process flow for a deep sub-micron technology
TAIWAN SEMICONDUCTOR MFG37 citations92
US5953601ASep 14, 1999
ESD implantation scheme for 0.35 μm 3.3V 70A gate oxide process
TAIWAN SEMICONDUCTOR MFG25 citations92
US5781445AJul 14, 1998
Plasma damage monitor
TAIWAN SEMICONDUCTOR MFG40 citations92
US6140693AOct 31, 2000
Method for making metal capacitors for deep submicrometer processes for semiconductor integrated circuits
TAIWAN SEMICONDUCTOR MFG34 citations91
US6451679B1Sep 17, 2002
Ion mixing between two-step titanium deposition process for titanium salicide CMOS technology
TAIWAN SEMICONDUCTOR MFG32 citations90
US7323784B2Jan 29, 2008
Top via pattern for bond pad structure
TAIWAN SEMICONDUCTOR MFG14 citations82
US6875682B1Apr 5, 2005
Mesh pad structure to eliminate IMD crack on pad
TAIWAN SEMICONDUCTOR MFG10 citations72
US7759797B2Jul 20, 2010
Bonding pad structure to minimize IMD cracking
TAIWAN SEMICONDUCTOR MFG1 citations61
US7135395B2Nov 14, 2006
Bonding pad structure to minimize IMD cracking
TAIWAN SEMICONDUCTOR MFG2 citations61