Inventor
GRUNER FRED
US25 patents
⚠️ This page may combine multiple inventors who share the name “GRUNER FRED”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
JUNIPER NETWORKS INC
13 patentsUS6880049B2Apr 12, 2005
Sharing a second tier cache memory in a multi-processor
JUNIPER NETWORKS INC139 citations99
US6754774B2Jun 22, 2004
Streaming output engine facilitating data transfers between application engines and memory
JUNIPER NETWORKS INC126 citations99
US6901482B2May 31, 2005
Managing ownership of a full cache line using a store-create operation
JUNIPER NETWORKS INC40 citations96
US6839808B2Jan 4, 2005
Processing cluster having multiple compute engines and shared tier one caches
JUNIPER NETWORKS INC35 citations94
US7068603B2Jun 27, 2006
Cross-bar switch
JUNIPER NETWORKS INC13 citations92
US6901489B2May 31, 2005
Streaming input engine facilitating data transfers between application engines and memory
JUNIPER NETWORKS INC12 citations92
US6901488B2May 31, 2005
Compute engine employing a coprocessor
JUNIPER NETWORKS INC11 citations82
US7170902B2Jan 30, 2007
Cross-bar switch incorporating a sink port with retry capability
JUNIPER NETWORKS INC4 citations74
US7123585B2Oct 17, 2006
Cross-bar switch with bandwidth allocation
JUNIPER NETWORKS INC4 citations74
US6920529B2Jul 19, 2005
Transferring data between cache memory and a media access controller
JUNIPER NETWORKS INC2 citations74
US6862669B2Mar 1, 2005
First tier cache memory preventing stale data storage
JUNIPER NETWORKS INC2 citations73
US7813364B2Oct 12, 2010
Cross-bar switch incorporating a sink port with retry capability
JUNIPER NETWORKS INC0 citations52
US7733905B2Jun 8, 2010
Cross-bar switch having bandwidth allocation
JUNIPER NETWORKS INC0 citations52
INTEL CORP
5 patentsUS6032278AFeb 29, 2000
Method and apparatus for performing scan testing
INTEL CORP26 citations90
US7213129B1May 1, 2007
Method and system for a two stage pipelined instruction decode and alignment using previous instruction length
INTEL CORP9 citations73
US6684322B1Jan 27, 2004
Method and system for instruction length decode
INTEL CORP9 citations73
US5978944ANov 2, 1999
Method and apparatus for scan testing dynamic circuits
INTEL CORP15 citations71
US5872795AFeb 16, 1999
Method and apparatus for scan testing of multi-phase logic
INTEL CORP6 citations60
GRUNER FRED
4 patentsUS8301980B2Oct 30, 2012
Error detection and correction for external DRAM
GRUNER FRED19 citations91
US8321761B1Nov 27, 2012
ECC bits used as additional register file storage
GRUNER FRED9 citations82
US8250439B1Aug 21, 2012
ECC bits used as additional register file storage
GRUNER FRED2 citations61
US8190974B2May 29, 2012
Error detection and correction for external DRAM
GRUNER FRED3 citations61