Inventor
SCHEER ROBERT F
US10 patents
Patents
10 patentsUS6303413B1Oct 16, 2001
Method of forming a shallow and deep trench isolation (SDTI) suitable for silicon on insulator (SOI) substrates
MAXIM INTEGRATED PRODUCTS61 citations94
US6686250B1Feb 3, 2004
Method of forming self-aligned bipolar transistor
MAXIM INTEGRATED PRODUCTS38 citations91
US6767798B2Jul 27, 2004
Method of forming self-aligned NPN transistor with raised extrinsic base
MAXIM INTEGRATED PRODUCTS32 citations90
US6475873B1Nov 5, 2002
Method of forming laser trimmable thin-film resistors in a fully planarized integrated circuit technology
MAXIM INTEGRATED PRODUCTS14 citations84
US6489217B1Dec 3, 2002
Method of forming an integrated circuit on a low loss substrate
MAXIM INTEGRATED PRODUCTS18 citations83
US7026666B2Apr 11, 2006
Self-aligned NPN transistor with raised extrinsic base
MAXIM INTEGRATED PRODUCTS11 citations80
US6855585B1Feb 15, 2005
Integrating multiple thin film resistors
MAXIM INTEGRATED PRODUCTS15 citations79
US6492237B2Dec 10, 2002
Method of forming an NPN device
MAXIM INTEGRATED PRODUCTS7 citations73
US6861324B2Mar 1, 2005
Method of forming a super self-aligned hetero-junction bipolar transistor
MAXIM INTEGRATED PRODUCTS10 citations72
US6593200B2Jul 15, 2003
Method of forming an integrated inductor and high speed interconnect in a planarized process with shallow trench isolation
MAXIM INTEGRATED PRODUCTS1 citations50