Inventor

PATEL RAKESH H

US98 patents

⚠️ This page may combine multiple inventors who share the name “PATEL RAKESH H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PATEL RAKESH H

ALTERA CORP

I/O buffer circuit with pin multiplexing

Look-up table based logic element with complete permutability of the inputs to the secondary signals

I/O buffer circuit with pin multiplexing

Partially reconfigurable programmable logic device

Programmable interconnect junction

Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers

Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements

Macrocell with flexible product term allocation

Integrated circuit output driver circuitry with programmable preemphasis

Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions

Programmable logic device having embedded dual-port random access memory configurable as single-port memory

Programmable logic device with redundant circuitry

Stacked die network-on-chip for FPGA

Circuitry for a low internal voltage integrated circuit

Overvoltage-tolerant interface for integrated circuits

Overvoltage-tolerant interface for integrated circuits

PLD with on-chip memory having a shadow register

Interface for low-voltage semiconductor devices

FPGA with on-chip multiport memory

Overvoltage-tolerant interface for intergrated circuits

Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions

Overvoltage-tolerant interface for integrated circuits

Interface for low-voltage semiconductor devices

Sample and load scheme for observability of internal nodes in a PLD

Programmable logic device with multi-port memory

Programmable logic device with multi-port memory

Diagnostic interface system for programmable logic system development

Look-up table based logic element with complete permutability of the inputs to the secondary signals

Sample and load scheme for observability of internal nodes in a PLD

Programmable logic with lower internal voltage circuitry

Programming programmable transistor devices using state machines

High-performance programmable logic architecture

Control pin for specifying integrated circuit voltage levels

Interface for low-voltage semiconductor devices

Sample and load scheme for observability internal nodes in a PLD

Input/output buffer with overcurrent protection circuit

Programmable tco circuit

I/O cell for programmable logic device providing latched, unlatched, and fast inputs

Systems and methods for simulating link performance

Apparatus for all-digital serializer-de-serializer and associated methods

Comparator offset cancellation assisted by PLD resources

Programmable logic device multispeed I/O circuitry

Integrated circuit output driver circuitry with programmable preemphasis

Programmable logic device multispeed I/O circuitry

Circuitry for a low internal voltage

Method of margin testing programmable interconnect cell

Method and apparatus for monitoring or forcing an internal node in a programmable device

Programming programmable transistor devices using state machines

PATEL RAKESH H

Stacked semiconductor substrates

CHOW FRANCIS MAN-CHIT

Stacked die network-on-chip for FPGA