Inventor
JAGANNATHAN BASANTH
US24 patents
⚠️ This page may combine multiple inventors who share the name “JAGANNATHAN BASANTH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
21 patentsUS7183576B2Feb 27, 2007
Epitaxial and polycrystalline growth of Si1-x-yGexCy and Si1-yCy alloy layers on Si by UHV-CVD
IBM14 citations92
US6875279B2Apr 5, 2005
Single reactor, multi-pressure chemical vapor deposition for semiconductor devices
IBM44 citations92
US6858532B2Feb 22, 2005
Low defect pre-emitter and pre-base oxide etch for bipolar transistors and related tooling
IBM44 citations92
US6787427B2Sep 7, 2004
Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics
IBM17 citations92
US6780695B1Aug 24, 2004
BiCMOS integration scheme with raised extrinsic base
IBM24 citations92
US6750119B2Jun 15, 2004
Epitaxial and polycrystalline growth of Si1-x-yGexCy and Si1-yCy alloy layers on Si by UHV-CVD
IBM22 citations92
US6744079B2Jun 1, 2004
Optimized blocking impurity placement for SiGe HBTs
IBM19 citations92
US6656809B2Dec 2, 2003
Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics
IBM40 citations92
US6426265B1Jul 30, 2002
Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
IBM25 citations92
US6927476B2Aug 9, 2005
Bipolar device having shallow junction raised extrinsic base and method for making the same
IBM16 citations84
US6506656B2Jan 14, 2003
Stepped collector implant and method for fabrication
IBM18 citations84
US6908866B2Jun 21, 2005
Epitaxial and polycrystalline growth of Si1-x-yGexCy and Si1-yCy alloy layers on Si by UHV-CVD
IBM6 citations73
US6780735B2Aug 24, 2004
Method to increase carbon and boron doping concentrations in Si and SiGe films
IBM7 citations73
US6815802B2Nov 9, 2004
Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
IBM5 citations71
US7741857B2Jun 22, 2010
System and method for de-embedding a device under test employing a parametrized netlist
IBM6 citations63
US6660607B2Dec 9, 2003
Method for fabricating heterojunction bipolar transistors
IBM2 citations63
US7713829B2May 11, 2010
Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
IBM1 citations62
US7355221B2Apr 8, 2008
Field effect transistor having an asymmetrically stressed channel region
IBM3 citations61
US6881259B1Apr 19, 2005
In-situ monitoring and control of germanium profile in silicon-germanium alloy films and temperature monitoring during deposition of silicon films
IBM1 citations52
US7173274B2Feb 6, 2007
Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
IBM0 citations51
US11916384B2Feb 27, 2024
Region-based power grid generation through modification of an initial power grid based on timing analysis
IBM0 citations48