Inventor

PURI RUCHIR

US73 patents

⚠️ This page may combine multiple inventors who share the name “PURI RUCHIR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PURI RUCHIR

IBM

Automatic correction of indirect bias in machine learning models

Wafer level I/O test, repair and/or customization enabled by I/O layer

Wafer level I/O test and repair enabled by I/O layer

Design stage mitigation of interconnect variability

Single supply level converter

Multiple voltage integrated circuit and design method therefor

Clock tree distribution generation by determining allowed placement regions for clocked elements

Matrix ordering for cache efficiency in performing large sparse matrix operations

Single supply level converter

Logic circuit for true and complement signal generator

System, method, and recording medium for mirroring matrices for batched Cholesky decomposition on a graphic processing unit

System, Method, and recording medium for mirroring matrices for batched Cholesky decomposition on a graphic processing unit

System, method, and recording medium for mirroring matrices for batched Cholesky decomposition on a graphic processing unit

System, method, and recording medium for mirroring matrices for batched cholesky decomposition on a graphic processing unit

Clock power minimization with regular physical placement of clock repeater components

Influence-based circuit design

Multiple voltage integrated circuit and design method therefor

Method and program product of level converter optimization

Automated synthesis of high-performance two operand binary parallel prefix adder

System and method for fast interconnect delay estimation through iterative refinement

Radix sort acceleration using custom asic

Concept analysis operations utilizing accelerators

Parallel quicksort

Radix sort acceleration using custom ASIC

System, method, and recording medium for mirroring matrices for batched cholesky decomposition on a graphic processing unit

Method for reducing wiring congestion in a VLSI chip design

Identifying candidate nodes for phase assignment in a logic network

Identifying an optimizable logic region in a logic network

Selecting phase assignments for candidate nodes in a logic network

Logic modification synthesis

Model agnostic contrastive explanations for structured data

Mirroring matrices for batched cholesky decomposition on a graphic processing unit

Concept analysis operations utilizing accelerators

Parallelized in-place radix sorting

System, method and computer program product for accelerating iterative graph algorithms by memory layout optimization

Parallel quicksort

Matrix ordering for cache efficiency in performing large sparse matrix operations

System, method and computer program product for accelerating iterative graph algorithms by memory layout optimization

System and method for global circuit routing incorporating estimation of critical area estimate metrics

Integrated circuit (IC) chip design method, program product and system

Three-dimensional cascaded power distribution in a semiconductor device

CHO MINSIK

Converged large block and structured synthesis for high performance microprocessor designs

Soft hierarchy-based physical synthesis for large-scale, high-performance circuits

Structured latch and local-clock-buffer planning

UNIV TECHNOLOGIES INT

Methodology and apparatus for modular partitioning for the machine design of asynchronous circuits

AMUNDSON MICHAEL D

Specifying circuit level connectivity during circuit design synthesis

GLOBALFOUNDRIES INC

Mapping a lookup table to prefabricated TCAMS

BECKER WIREN DALE

Network flow based module bottom surface metal pin assignment

PURI RUCHIR

Regular local clock buffer placement and latch clustering by iterative optimization

FLEISCHER BRUCE M

Automated critical area allocation in a physical synthesized hierarchical design