Inventor

REN HAOXING

US45 patents

⚠️ This page may combine multiple inventors who share the name “REN HAOXING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

REN HAOXING

IBM

Integrated circuit design changes using through-silicon vias

Clock aware placement

Method for successive placement based refinement of a generalized cost function

Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors

Flow based package pin assignment

Constrained detailed placement

Automating a microarchitecture design exploration environment

Method and apparatus for diffusion based cell placement migration

Integrated circuit design changes using through-silicon vias

Integrated circuit design changes using through-silicon vias

Integrated circuit design changes using through-silicon vias

LLVM-based system C compiler for architecture synthesis

Automating a microarchitecture design exploration environment

Logic modification synthesis

Apparatus and method for improved test controllability and observability of random resistant logic

Through-silicon via access device for integrated circuits

Through-silicon via access device for integrated circuits

Placement aware functional engineering change order extraction

Automating a microarchitecture design exploration environment

Synthesis for random testability using unreachable states in integrated circuits

NVIDIA CORP

Deep learning testability analysis with graph convolutional networks

Fine-grained per-vector scaling for neural network quantization

Fine-grained per-vector scaling for neural network quantization

Layout parasitics and device parameter prediction using graph neural networks

VLSI placement optimization using self-supervised graph clustering

Rail power density aware standard cell placement for integrated circuits

Standard cell layout generation with applied artificial intelligence

IR drop prediction with maximum convolutional neural network

Lithography simulation using a neural network

Techniques for generating designs of circuits that include buffers using machine learning

Reducing crosstalk pessimism using GPU-accelerated gate simulation and machine learning

Layout parasitics and device parameter prediction using graph neural networks

Rail power density aware standard cell placement for integrated circuits

Routing connections in integrated circuits based on reinforcement learning

Determining IR drop

CHO MINSIK

Converged large block and structured synthesis for high performance microprocessor designs

Soft hierarchy-based physical synthesis for large-scale, high-performance circuits

Structured latch and local-clock-buffer planning

Relative ordering circuit synthesis

BECKER WIREN DALE

Network flow based module bottom surface metal pin assignment

FLEISCHER BRUCE M

Automated critical area allocation in a physical synthesized hierarchical design

XIANG HUA

Network flow based datapath bit slicing

ALPERT CHARLES J

System and computer program product for diffusion based cell placement migration

HOPKINS JEREMY T

Logic difference synthesis

REN HAOXING

Logic modification synthesis for high performance circuits