Inventor
ZIEGLER MATTHEW M
US19 patents
⚠️ This page may combine multiple inventors who share the name “ZIEGLER MATTHEW M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
14 patentsUS10083268B2Sep 25, 2018
Scheduling simultaneous optimization of multiple very-large-scale-integration designs
IBM6 citations83
US9600623B1Mar 21, 2017
Scheduling simultaneous optimization of multiple very-large-scale-integration designs
IBM5 citations83
US9529951B2Dec 27, 2016
Synthesis tuning system for VLSI design optimization
IBM7 citations82
US10002221B2Jun 19, 2018
Enhanced parameter tuning for very-large-scale integration synthesis
IBM2 citations72
US9934344B2Apr 3, 2018
Enhanced parameter tuning for very-large-scale integration synthesis
IBM3 citations72
US9703920B2Jul 11, 2017
Intra-run design decision process for circuit synthesis
IBM3 citations72
US9910949B2Mar 6, 2018
Synthesis tuning system for VLSI design optimization
IBM2 citations71
US9619602B2Apr 11, 2017
Enhanced parameter tuning for very-large-scale integration synthesis
IBM1 citations61
US10263519B2Apr 16, 2019
Resonant virtual supply booster for synchronous digital circuits having a predictable evaluate time
IBM0 citations52
US9660530B2May 23, 2017
Resonant virtual supply booster for synchronous digital circuits having a predictable evaluate time
IBM0 citations52
US10789400B2Sep 29, 2020
Scheduling simultaneous optimization of multiple very-large-scale-integration designs
IBM0 citations51
US9690900B2Jun 27, 2017
Intra-run design decision process for circuit synthesis
IBM0 citations51
US9582627B2Feb 28, 2017
Enhanced parameter tuning for very-large-scale integration synthesis
IBM0 citations51
US8954914B2Feb 10, 2015
Graphical method and product to assign physical attributes to entities in a high level descriptive language used for VLSI chip design
IBM1 citations49
CHO MINSIK
3 patentsUS8271920B2Sep 18, 2012
Converged large block and structured synthesis for high performance microprocessor designs
CHO MINSIK34 citations90
US8516412B2Aug 20, 2013
Soft hierarchy-based physical synthesis for large-scale, high-performance circuits
CHO MINSIK8 citations83
US8495552B1Jul 23, 2013
Structured latch and local-clock-buffer planning
CHO MINSIK13 citations83