Inventor
BIGBEE BRYANT E
US23 patents
⚠️ This page may combine multiple inventors who share the name “BIGBEE BRYANT E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
15 patentsUS6349380B1Feb 19, 2002
Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor
INTEL CORP91 citations98
US8010969B2Aug 30, 2011
Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers
INTEL CORP16 citations92
US6920581B2Jul 19, 2005
Method and apparatus for functional redundancy check mode recovery
INTEL CORP29 citations92
US10162694B2Dec 25, 2018
Hardware apparatuses and methods for memory corruption detection
INTEL CORP12 citations84
US6289431B1Sep 11, 2001
Method and apparatus for accessing more than 4 Gigabytes of physical memory with 4-byte table entries
INTEL CORP17 citations84
US11645135B2May 9, 2023
Hardware apparatuses and methods for memory corruption detection
INTEL CORP1 citations73
US10275598B2Apr 30, 2019
Providing a secure execution mode in a pre-boot environment
INTEL CORP3 citations73
US6857066B2Feb 15, 2005
Apparatus and method to identify the maximum operating frequency of a processor
INTEL CORP7 citations73
US5946713AAug 31, 1999
Memory attribute palette
INTEL CORP8 citations73
US9448829B2Sep 20, 2016
Hetergeneous processor apparatus and method
INTEL CORP2 citations62
US6898700B2May 24, 2005
Efficient saving and restoring state in task switching
INTEL CORP6 citations61
US10776190B2Sep 15, 2020
Hardware apparatuses and methods for memory corruption detection
INTEL CORP0 citations52
US9069605B2Jun 30, 2015
Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention
INTEL CORP1 citations52
US10452403B2Oct 22, 2019
Mechanism for instruction set based thread execution on a plurality of instruction sequencers
INTEL CORP0 citations51
US9063804B2Jun 23, 2015
System to profile and optimize user software in a managed run-time environment
INTEL CORP0 citations51
NEWBURN CHRIS J
3 patentsUS8301868B2Oct 30, 2012
System to profile and optimize user software in a managed run-time environment
NEWBURN CHRIS J15 citations91
US8171268B2May 1, 2012
Technique for context state management to reduce save and restore operations between a memory and a processor using in-use vectors
NEWBURN CHRIS J7 citations83
US8566567B2Oct 22, 2013
System to profile and optimize user software in a managed run-time environment
NEWBURN CHRIS J0 citations51
HANKINS RICHARD A
2 patentsUS8887174B2Nov 11, 2014
Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers
HANKINS RICHARD A2 citations61
US8607235B2Dec 10, 2013
Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention
HANKINS RICHARD A3 citations61