Inventor

ATHREYA ARUN SITARAM

US3 patents

Patents

3 patents

US11769557B2Sep 26, 2023

Techniques for preventing read disturb in NAND memory

INTEL CORP2 citations71

US12094545B2Sep 17, 2024

Techniques for preventing read disturb in NAND memory

INTEL CORP0 citations60

US11302405B2Apr 12, 2022

System approach to reduce stable threshold voltage (Vt) read disturb degradation

INTEL CORP0 citations59