Inventor

OGANESIAN VAGE

US136 patents

⚠️ This page may combine multiple inventors who share the name “OGANESIAN VAGE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OGANESIAN VAGE

OGANESIAN VAGE

Microelectronic elements with post-assembly planarization

Microelectronic elements having metallic pads overlying vias

Active chip on carrier or laminated chip having microelectronic element embedded therein

Microelectronic elements with rear contacts connected with via first or via middle structures

Stacked microelectronic assemby with TSVS formed in stages and carrier above chip

Multi-function and shielded 3D interconnects

Low stress cavity package for back side illuminated image sensor, and method of making same

High density three-dimensional integrated capacitors

Wire bond interposer package for CMOS image sensor and method of making same

Method of making stamped multi-layer polymer lens

Carrier structures for microelectronic elements

Stepped package for image sensor and method of making same

Staged via formation from both sides of chip

Interposer package for CMOS image sensor and method of making same

Low profile image sensor package

Non-lithographic formation of three-dimensional conductive elements

Back side illuminated image sensor architecture, and method of making same

Chip assembly having via interconnects joined by plating

Compliant interconnects in wafers

Multi-layer polymer lens and method of making same

3D integrated microelectronic assembly with stress reducing interconnects

3D integration microelectronic assembly for integrated circuit devices

TESSERA INC

Reconstituted wafer level stacking

Edge connect wafer level stacking

Edge connect wafer level stacking

Packaged semiconductor chips

Systems and methods for producing flat surfaces in interconnect structures

Systems and methods for producing flat surfaces in interconnect structures

High density three-dimensional integrated capacitors

High density three-dimensional integrated capacitors

High density three-dimensional integrated capacitors

Multi-function and shielded 3D interconnects

Stacked microelectronic assembly with TSVS formed in stages and carrier above chip

Simultaneous wafer bonding and interconnect joining

TESSERA TECH HUNGARY KFT

Methods and apparatus for packaging integrated circuit devices

Methods and apparatus for packaging integrated circuit devices

Methods and apparatus for packaging integrated circuit devices

Methods and apparatus for packaging integrated circuit devices

Wafer-level fabrication of lidded chips with electrodeposited dielectric coating

Methods and apparatus for packaging integrated circuit devices

HABA BELGACEM

Off-chip vias in stacked chips

Chips having rear contacts connected by through vias to front contacts

Chips having rear contacts connected by through vias to front contacts

Stacked microelectronic assembly having interposer connecting active chips

TESSERA TECH IRELAND LTD

Wafer-level fabrication of lidded chips with electrodeposited dielectric coating

Wafer level chip packaging

UZOH CYPRIAN

Systems and methods for producing flat surfaces in interconnect structures

Electrical barrier layers

SHELLCASE LTD

Methods and apparatus for packaging integrated circuit devices

MOHAMMED ILYAS

High density three-dimensional integrated capacitors