Inventor

SAVALIA PIYUSH

US59 patents

⚠️ This page may combine multiple inventors who share the name “SAVALIA PIYUSH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAVALIA PIYUSH

TESSERA INC

High density three-dimensional integrated capacitors

High density three-dimensional integrated capacitors

High density three-dimensional integrated capacitors

Multi-function and shielded 3D interconnects

Stacked microelectronic assembly with TSVS formed in stages and carrier above chip

Simultaneous wafer bonding and interconnect joining

High density three-dimensional integrated capacitors

Staged via formation from both sides of chip

Active chip on carrier or laminated chip having microelectronic element embedded therein

Laminated chip having microelectronic element embedded therein

Staged via formation from both sides of chip

Stacked microelectronic assembly with TSVS formed in stages and carrier above chip

Electrical barrier layers

Vias in porous substrates

Multi-chip module with stacked face-down connected dies

Microelectronic elements with post-assembly planarization

Staged via formation from both sides of chip

High density three-dimensional integrated capacitors

Stacked microelectronic assembly with TSVS formed in stages with plural active chips

Non-lithographic formation of three-dimensional conductive elements

Compliant interconnects in wafers

Microelectronic elements with post-assembly planarization

Microelectronic elements with post-assembly planarization

Multi-chip module with stacked face-down connected dies

Stacked microelectronic assembly with TSVs formed in stages with plural active chips

Active chip on carrier or laminated chip having microelectronic element embedded therein

Non-lithographic formation of three-dimensional conductive elements

OGANESIAN VAGE

Microelectronic elements with post-assembly planarization

Microelectronic elements having metallic pads overlying vias

Active chip on carrier or laminated chip having microelectronic element embedded therein

Microelectronic elements with rear contacts connected with via first or via middle structures

Stacked microelectronic assemby with TSVS formed in stages and carrier above chip

Multi-function and shielded 3D interconnects

High density three-dimensional integrated capacitors

Carrier structures for microelectronic elements

Staged via formation from both sides of chip

Non-lithographic formation of three-dimensional conductive elements

Chip assembly having via interconnects joined by plating

Compliant interconnects in wafers

Simultaneous wafer bonding and interconnect joining

BSI image sensor package with embedded absorber for even reception of different wavelengths

BSI image sensor package with variable-height silicon for even reception of different wavelengths

Stacked microelectronic assembly with TSVs formed in stages with plural active chips

HABA BELGACEM

Multi-chip module with stacked face-down connected dies

Stacked microelectronic assembly having interposer connecting active chips

MOHAMMED ILYAS

High density three-dimensional integrated capacitors

Vias in porous substrates

JEWELL-LARSEN NELS

Electrohydrodynamic fluid accelerator device with collector electrode exhibiting curved leading edge profile

Electrohydrodynamic fluid accelerator with heat transfer surfaces operable as collector electrode

UZOH CYPRIAN

Electrical barrier layers