Inventor

HOWER PHILIP L

US43 patents

⚠️ This page may combine multiple inventors who share the name “HOWER PHILIP L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOWER PHILIP L

TEXAS INSTRUMENTS INC

N-channel LDMOS with buried P-type region to prevent parasitic bipolar effects

N-channel LDMOS with buried p-type region to prevent parasitic bipolar effects

Vertical thermoelectric structures

Integrated lateral high voltage MOSFET

ESD robust bipolar transistor with high variable trigger and sustaining voltages

Premature breakdown in submicron device geometries

Distributed high voltage JFET

Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor

Isolation trench with rounded corners for BiCMOS process

Segmented power MOSFET of safe operation

Lateral MOSFET with buried drain extension layer

Lateral MOSFET with buried drain extension layer

Integrated high-side driver for P-N bimodal power device

Transistor having double isolation with one floating isolation

Distributed high voltage JFET

Lateral MOSFET with buried drain extension layer

IC with floating buried layer ring for isolation of embedded islands

Integration of high voltage JFET in linear bipolar CMOS process

Distributed power MOSFET

Transistor with improved safe operating area

Integrated circuit having a top side wafer contact and a method of manufacture therefor

High voltage depletion FET employing a channel stopping implant

Integrated high-side driver for P-N bimodal power device

Lateral MOSFET with buried drain extension layer

Vertical thermoelectric structures

Structures to avoid floating resurf layer in high voltage lateral devices

Structures to avoid floating RESURF layer in high voltage lateral devices

Distributed high voltage JFET

Integrated circuit having a top side wafer contact and a method of manufacture therefor

UNITRODE CORP

New diode structure

Structure for fast-recovery bipolar devices

Method for reducing leakage currents in semiconductor devices

DENISON MARIE

Method of making vertical transistor with graded field plate dielectric

Integrated lateral high voltage MOSFET

High voltage drain extension on thin buried oxide SOI

WESTINGHOUSE ELECTRIC CORP

Technique for controlling emitter ballast resistance

High voltage transistor with high gain

KAWAHARA HIDEAKI

Integrated high voltage divider

Integrated gate controlled high voltage divider

MALE BARRY JON

Vertical thermoelectric structures

ELECTRIC POWER RES INST

Method for the nondestructive testing of voltage limiting blocks

PENDHARKAR SAMEER P

Isolation trench with rounded corners for BiCMOS process

HOWER PHILIP L

Circuit having integrated heating structure for parametric trimming