Inventor
SATOH KIMIHIRO
US63 patents
⚠️ This page may combine multiple inventors who share the name “SATOH KIMIHIRO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
AVALANCHE TECHNOLOGY INC
20 patentsUS9166154B2Oct 20, 2015
MTJ stack and bottom electrode patterning process with ion beam etching using a single mask
AVALANCHE TECHNOLOGY INC47 citations94
US9070869B2Jun 30, 2015
Fabrication method for high-density MRAM using thin hard mask
AVALANCHE TECHNOLOGY INC29 citations94
US8975089B1Mar 10, 2015
Method for forming MTJ memory element
AVALANCHE TECHNOLOGY INC40 citations94
US8962349B1Feb 24, 2015
Method of manufacturing magnetic tunnel junction memory element
AVALANCHE TECHNOLOGY INC38 citations94
US8975088B2Mar 10, 2015
MRAM etching processes
AVALANCHE TECHNOLOGY INC22 citations92
US8724380B1May 13, 2014
Method for reading and writing multi-level cells
AVALANCHE TECHNOLOGY INC22 citations92
US9373663B2Jun 21, 2016
Landing pad in peripheral circuit for magnetic random access memory (MRAM)
AVALANCHE TECHNOLOGY INC9 citations84
US9029822B2May 12, 2015
High density resistive memory having a vertical dual channel transistor
AVALANCHE TECHNOLOGY INC9 citations84
US9013045B2Apr 21, 2015
MRAM with sidewall protection and method of fabrication
AVALANCHE TECHNOLOGY INC11 citations84
US8878156B2Nov 4, 2014
Memory device having stitched arrays of 4 F2 memory cells
AVALANCHE TECHNOLOGY INC8 citations84
US9812499B1Nov 7, 2017
Memory device incorporating selector element with multiple thresholds
AVALANCHE TECHNOLOGY INC14 citations83
US10224367B2Mar 5, 2019
Selector device incorporating conductive clusters for memory applications
AVALANCHE TECHNOLOGY INC3 citations73
US10153017B2Dec 11, 2018
Method for sensing memory element coupled to selector device
AVALANCHE TECHNOLOGY INC6 citations73
US9647032B2May 9, 2017
Spin-orbitronics device and applications thereof
AVALANCHE TECHNOLOGY INC4 citations73
US9627438B1Apr 18, 2017
Three dimensional memory arrays and stitching thereof
AVALANCHE TECHNOLOGY INC5 citations73
US9548448B1Jan 17, 2017
Memory device with increased separation between memory elements
AVALANCHE TECHNOLOGY INC2 citations73
US9123575B1Sep 1, 2015
Semiconductor memory device having increased separation between memory elements
AVALANCHE TECHNOLOGY INC5 citations73
US10522590B2Dec 31, 2019
Magnetic memory incorporating dual selectors
AVALANCHE TECHNOLOGY INC2 citations72
US9209390B2Dec 8, 2015
Memory device having stitched arrays of 4 F2 memory cells
AVALANCHE TECHNOLOGY INC3 citations63
US9029824B2May 12, 2015
Memory device having stitched arrays of 4 F2 memory cells
AVALANCHE TECHNOLOGY INC2 citations63
HALO LSI INC
18 patentsUS6670240B2Dec 30, 2003
Twin NAND device structure, array operations and fabrication method
HALO LSI INC124 citations99
US6900098B1May 31, 2005
Twin insulator charge storage device operation and its fabrication method
HALO LSI INC33 citations96
US6756271B1Jun 29, 2004
Simplified twin monos fabrication method with three extra masks to standard CMOS
HALO LSI INC64 citations96
US7006378B1Feb 28, 2006
Array architecture and operation methods for a nonvolatile memory
HALO LSI INC31 citations93
US6825084B2Nov 30, 2004
Twin NAND device structure, array operations and fabrication method
HALO LSI INC25 citations93
US6759290B2Jul 6, 2004
Stitch and select implementation in twin MONOS array
HALO LSI INC31 citations93
US7394703B2Jul 1, 2008
Twin insulator charge storage device operation and its fabrication method
HALO LSI INC12 citations84
US7170132B2Jan 30, 2007
Twin insulator charge storage device operation and its fabrication method
HALO LSI INC10 citations84
US7411247B2Aug 12, 2008
Twin insulator charge storage device operation and its fabrication method
HALO LSI INC5 citations74
US7382659B2Jun 3, 2008
Twin insulator charge storage device operation and its fabrication method
HALO LSI INC6 citations74
US7382662B2Jun 3, 2008
Twin insulator charge storage device operation and its fabrication method
HALO LSI INC4 citations74
US7359250B2Apr 15, 2008
Twin insulator charge storage device operation and its fabrication method
HALO LSI INC6 citations74
US7352033B2Apr 1, 2008
Twin MONOS array for high speed application
HALO LSI INC8 citations74
US7046556B2May 16, 2006
Twin insulator charge storage device operation and its fabrication method
HALO LSI INC4 citations74
US6838344B2Jan 4, 2005
Simplified twin monos fabrication method with three extra masks to standard CMOS
HALO LSI INC8 citations74
US7391653B2Jun 24, 2008
Twin insulator charge storage device operation and its fabrication method
HALO LSI INC5 citations63
US7118961B2Oct 10, 2006
Stitch and select implementation in twin MONOS array
HALO LSI INC3 citations63
US6998658B2Feb 14, 2006
Twin NAND device structure, array operations and fabrication method
HALO LSI INC1 citations63
SATOH KIMIHIRO
9 patentsUS8883520B2Nov 11, 2014
Redeposition control in MRAM fabrication process
SATOH KIMIHIRO72 citations98
US8574928B2Nov 5, 2013
MRAM fabrication method with sidewall cleaning
SATOH KIMIHIRO131 citations98
US8796795B2Aug 5, 2014
MRAM with sidewall protection and method of fabrication
SATOH KIMIHIRO23 citations92
US8709956B2Apr 29, 2014
MRAM with sidewall protection and method of fabrication
SATOH KIMIHIRO20 citations92
US8575584B2Nov 5, 2013
Resistive memory device having vertical transistors and method for making the same
SATOH KIMIHIRO25 citations92
US8536063B2Sep 17, 2013
MRAM etching processes
SATOH KIMIHIRO21 citations92
US9082695B2Jul 14, 2015
Vialess memory structure and method of manufacturing same
SATOH KIMIHIRO4 citations73
US8633544B2Jan 21, 2014
Twin MONOS array for high speed application
SATOH KIMIHIRO4 citations73
US8081515B2Dec 20, 2011
Trench monos memory cell and array
SATOH KIMIHIRO4 citations63
JUNG DONG HA
1 patentHALO INC
1 patentMALMHALL ROGER KLAS
1 patentShowing the top 50 of 63 patents by PatentIndex Score.