Inventor

HUNTER HILLERY C

US77 patents

⚠️ This page may combine multiple inventors who share the name “HUNTER HILLERY C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUNTER HILLERY C

IBM

Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

Selective memory error reporting

Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

Advanced memory device having reduced power and improved performance

Error monitoring of a memory device containing embedded error correction

Thermal-aware memory

Error monitoring of a memory device containing embedded error correction

Thermal-aware memory

Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

Memory system connector

DRAM error detection, evaluation, and correction

DRAM error detection, evaluation, and correction

Method and apparatus for monitoring event occurrences

Error feedback and logging with memory on-chip error checking and correcting (ECC)

Nonvolatile memory data security

Method and system for integrating SRAM and DRAM architecture in set associative cache

Processor bus for performance monitoring with digests

Integrated wafer-level processing system

Detecting a cryogenic attack on a memory device with embedded error correction

Memory system with switchable operating bands

Processor with memory-embedded pipeline for table-driven computation

Memory device error history bit

Selective memory error reporting

Memory device error history bit

Error monitoring of a memory device containing embedded error correction

Interface clock frequency switching using a computed insertion delay

Securing the contents of a memory device

Nonvolatile memory data security

Adaptive error correction in a memory system

Error feedback and logging with memory on-chip error checking and correcting (ECC)

Data retrieval from stacked computer memory

Implementing selective cache injection

Securing the contents of a memory device

Implementing memory device with sub-bank architecture

Managing errors in a DRAM by weak cell encoding

Processor bus for performance monitoring with digests

Processor bus for performance monitoring with digests

Adaptive error correction in a memory system

DRAM controller for variable refresh operation timing

Method and system for implementing dynamic refresh protocols for DRAM based cache

System, method and computer program product for instantiating blocks of a solid-state disk to include different flash characteristics

KIM KYU-HYOUN

Advanced memory device having improved performance, reduced power and increased reliability

Advanced memory device having improved performance, reduced power and increased reliability

Advanced memory device having improved performance, reduced power and increased reliability

DALY DAVID M

Memory bus write prioritization

Coordinated writeback of dirty cachelines

GLOBALFOUNDRIES INC

Implementing reinforcement learning based flash control

FRANCESCHINI MICHELE M

Method for optimizing refresh rate for DRAM

HENDERSON JOAB D

Memory system with dynamic refreshing