Inventor

KILMER CHARLES A

US49 patents

⚠️ This page may combine multiple inventors who share the name “KILMER CHARLES A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KILMER CHARLES A

IBM

Selective memory error reporting

Advanced memory device having reduced power and improved performance

System and method for providing DRAM device-level repair via address remappings external to the device

Memory array system

Error monitoring of a memory device containing embedded error correction

Error monitoring of a memory device containing embedded error correction

Detecting defective connections in stacked memory devices

Memory system connector

Detecting defective connections in stacked memory devices

DRAM error detection, evaluation, and correction

DRAM error detection, evaluation, and correction

Error feedback and logging with memory on-chip error checking and correcting (ECC)

Nonvolatile memory data security

276-pin buffered memory module with enhanced memory system interconnect and features

Distributed serialized data buffer and a memory module for a cascadable and extended memory subsystem

Detecting a cryogenic attack on a memory device with embedded error correction

Memory device error history bit

Selective memory error reporting

Memory device error history bit

Error monitoring of a memory device containing embedded error correction

Securing the contents of a memory device

Implementing DRAM row hammer avoidance

Implementing DRAM row hammer avoidance

Nonvolatile memory data security

Adaptive error correction in a memory system

Error feedback and logging with memory on-chip error checking and correcting (ECC)

Accessing a resistive memory storage device

Securing the contents of a memory device

Implementing memory device with sub-bank architecture

Managing errors in a DRAM by weak cell encoding

Adaptive error correction in a memory system

Extended error correction coding data storage

Extended error correction coding data storage

Handling repaired memory array elements in a memory of a computer system

Error vector readout from a memory device

Error vector readout from a memory device

Accessing a resistive memory storage device

Managing errors in a DRAM by weak cell encoding

Hybrid latch and fuse scheme for memory repair

Hybrid latch and fuse scheme for memory repair

Adaptive error correction in a memory system

Dynamic random access memory with pseudo differential sensing

Error-correcting code distribution for memory systems

KIM KYU-HYOUN

Advanced memory device having improved performance, reduced power and increased reliability

Advanced memory device having improved performance, reduced power and increased reliability

Advanced memory device having improved performance, reduced power and increased reliability

FRANCESCHINI MICHELE M

Method for optimizing refresh rate for DRAM

DRAM refresh

KILMER CHARLES A

Memory system with a programmable refresh cycle