Inventor

LASTRAS-MONTANO LUIS A

US152 patents

⚠️ This page may combine multiple inventors who share the name “LASTRAS-MONTANO LUIS A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LASTRAS-MONTANO LUIS A

IBM

Heterogeneous recovery in a redundant memory system

Iterative write pausing techniques to improve read latency of memory systems

Systems and methods for error detection in a memory system

Cognitive operations based on empirically constructed knowledge graphs

Analyzing concepts over time

System and method for error correction and detection in a memory system

Systems and methods for improving serviceability of a memory system

Adaptive wear leveling via monitoring the properties of memory reference stream

System and method for providing a high fault tolerant memory system

System and method for providing DRAM device-level repair via address remappings external to the device

Error correction potency improvement via added burst beats in a dram access cycle

Automatically linking text to concepts in a knowledge base

Automatic new concept definition

Automatically linking text to concepts in a knowledge base

Automatically linking text to concepts in a knowledge base

Analyzing concepts over time

Analyzing concepts over time

Analyzing concepts over time

Computing the relevance of a document to concepts not specified in the document

Inverted table for storing and querying conceptual indices

User interface for summarizing the relevance of a document to a query

Computing the relevance of a document to concepts not specified in the document

Inverted table for storing and querying conceptual indices

Matrix ordering for cache efficiency in performing large sparse matrix operations

User interface for summarizing the relevance of a document to a query

DRAM error detection, evaluation, and correction

DRAM error detection, evaluation, and correction

System to improve memory failure management and associated methods

System and method for providing constrained transmission and storage in a random access memory

Iteratively writing contents to memory locations using a statistical model

Error control coding methods for memories with subline accesses

Concept hierarchies

Relation extraction using co-training with distant supervision

FRANCESCHINI MICHELE M

Adaptive endurance coding of non-volatile memories

Memory cell presetting for improved memory performance

Accessing coded data stored in a non-volatile memory

Probabilistic multi-tier error correction in not-and (NAND) flash memory

Non-volatile memories with enhanced write performance and endurance

Multi-write coding of non-volatile memories

ALVES LUIZ C

Correcting memory device and memory channel failures in the presence of known memory device failures

Error correction and detection in a redundant memory system

GLOBALFOUNDRIES INC

ECC bypass using low latency CE correction with retry select signal

ECC bypass using low latency CE correction with retry select signal

BREITWISCH MATTHEW J

Resistive memory devices having a not-and (NAND) structure

DALY DAVID M

Prediction based priority scheduling

O'CONNOR JAMES A

High availability memory system

LASTRAS-MONTANO LUIS A

Failing bus lane detection using syndrome analysis

ELFADEL IBRAHIM M

Adjustable write bins for multi-level analog memories

ABALI BULENT

Wear-leveling and bad block management of limited lifetime memory devices

DELL TIMOTHY J

System to improve error code decoding using historical information and associated methods