Inventor

BLANER BARTHOLOMEW

US106 patents

⚠️ This page may combine multiple inventors who share the name “BLANER BARTHOLOMEW”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BLANER BARTHOLOMEW

IBM

In-memory preprocessor for compounding a sequence of instructions for parallel computer system execution

Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit

Multiple condition code branching system in a multi-processor environment

Multi-function permutation switch for rotating and manipulating an order of bits of an input data byte in either cyclic or non-cyclic mode

Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism

System for obtaining parallel execution of existing instructions in a particulr data processing configuration by compounding rules based on instruction categories

Status predictor for combined shifter-rotate/merge unit

System for executing scalar instructions in parallel based on control bits appended by compounding decoder

System and method for obtaining parallel existing instructions in a particular data processing configuration by compounding instructions

Predecode instruction compounding

Apparatus for initializing branch prediction information

System for issuing instructions for parallel execution subsequent to branch into a group of member instructions with compoundability in dictation tag

Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel

Memory management for scalable compound instruction set machines with in-memory compounding

Data dependency collapsing hardware apparatus

Apparatus and method for implementing precise interrupts on a pipelined processor with multiple functional units with separate address translation interrupt means

Parallel huffman decoder

Method for processing instructions for parallel execution including storing instruction sequences along with compounding information in cache

Interleaved key memory with multi-page key cache

Cache store of instruction pairs with tags to indicate parallel execution

Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel

Packet switch network protocol

Data dependency collapsing hardware apparatus

Cross-cache-line compounding algorithm for scism processors

Computer system accelerator for multi-word cross-boundary storage access

Real time invariant behavior cache

Processing system and method for minimum/maximum number determination

Integrated circuit and data processing system having a configurable cache directory for an accelerator

Concurrent error detection in a ternary content-addressable memory (TCAM) device

Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elements

Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elements

Creating a dynamic Huffman table

Method and structure for low latency load-tagged pointer instruction for computer microarchitechture

Facilitating inter-DSP data communications

Facilitating inter-DSP data communications

Updating cache using two bloom filters

Apparatus and method for storing and initializing branch prediction with selective information transfer

Managing lowest point of coherency (LPC) memory using a service layer adapter

Pre-transmission data reordering for a serial interface

Operation of a multi-slice processor implementing priority encoding of data pattern matches

Concurrent error detection in a ternary content-addressable memory (TCAM) device

Coherent attached processor proxy having hybrid directory

Translation invalidation in a translation cache serving an accelerator

Tracking memory accesses when invalidating effective address to real address translations

Data recovery for coherent attached processor proxy

Cross-cache-line compounding algorithm for scism processors

Updating cache using two bloom filters

Techniques for improving random number generation security

BLANER BARTHOLOMEW

Method for predictive decoding of a load tagged pointer instruction

Structure for predictive decoding