Inventor

JAYARAMAN PRASANNA

IN53 patents

⚠️ This page may combine multiple inventors who share the name “JAYARAMAN PRASANNA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JAYARAMAN PRASANNA

IBM

Dynamically varying transfer size in a storage device for improved performance

Multiple level computer system for temperature management for cooling fan control

Virtual grouping of memory

Multiple level computer system temperature management for cooling fan control

Managing temperature of solid state disk devices

Managing temperature of solid state disk devices

Budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements

Transfer size monitor, determination, and optimization engine for storage devices

Budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements

Transfer size monitor, determination, and optimization engine for storage devices

Reconfigurable network infrastructure

Thermal control system based on nonlinear zonal fan operation and optimized fan power

Bus interface optimization by selecting bit-lanes having best performance margins

Characterization and validation of processor links

Memory data management

Staged power on/off sequence at the I/O phy level in an interchip interface

Managing temperature of solid state disk devices

Characterization and validation of processor links

Redundant voltage delivery with active cables

Architecture with micro-controller and high-speed active cables

Remapping software elements to increase the usability of a device with a damaged screen

Remapping software elements to increase the usability of a device with a damaged screen

Detecting cross-talk on processor links

System interconnect dynamic scaling handshake using spare bit-lane

System interconnect dynamic scaling handshake using spare bit-lane

System interconnect dynamic scaling by lane width and operating frequency balancing

System interconnect dynamic scaling by lane width and operating frequency balancing

Bus interface optimization by selecting bit-lanes having best performance margins

Allocating memory address space between DIMMs using memory controllers

System interconnect dynamic scaling by predicting I/O requirements

Allocating memory address space between DIMMs using memory controllers

System interconnect dynamic scaling by predicting I/O requirements

Implementing DRAM failure scenarios mitigation by using buffer techniques delaying usage of RAS features in computer systems

Memory transaction prioritization

Memory transaction prioritization

Managing temperature of solid state disk devices

Managing temperature of solid state disk devices

Managing temperature of solid state disk devices

Budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements

Dynamic prescaling for performance counters

Dynamic prescaling for performance counters

Implementing enhanced security with storing data in DRAMs

Implementing enhanced security with storing data in DRAMs

Frequency guard band validation of processors

Thermal control system based on nonlinear zonal fan operation and optimized fan power

BERRY JR ROBERT W

Characterization and validation of processor links

Frequency guard band validation of processors

Detecting cross-talk on processor links

LENOVO ENTPR SOLUTIONS SINGAPORE PTE LTD

Subsystem-level power management in a multi-node virtual machine environment

DUSANAPUDI MANOJ

Using a buffer to replace failed memory cells in a memory component