Inventor

CHIH YUE-DER

TW105 patents

⚠️ This page may combine multiple inventors who share the name “CHIH YUE-DER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHIH YUE-DER

TAIWAN SEMICONDUCTOR MFG CO LTD

Method and apparatus for MRAM sense reference trimming

Resistive random access memory device

Memory devices with improved refreshing operation

Charge pump

Semiconductor device structure and method for forming the same

Low dropout regulator and related method

Memory devices with improved refreshing operation

Method and apparatus for MRAM sense reference trimming

Memory devices with improved refreshing operations

Operating resistive memory cell

Memory device having RRAM-based non-volatile storage array

Fuse structure

MRAM smart bit write algorithm with error correction parity bits

Memory devices with improved refreshing operation

Memory controller, memory device and method of operating

Memory devices with improved refreshing operation

MRAM smart bit write algorithm with error correction parity bits

Semiconductor arrangement and formation thereof

Resistive memory array and fabricating method thereof

TAIWAN SEMICONDUCTOR MFG

Back-bias voltage regulator having temperature and process variation compensation and related method of regulating a back-bias voltage

Reference cell array to generate the reference current for sense amplifier

Low power charge pump regulating circuit

Products derived from embedded flash/EEPROM products

Accommodating balance of bit line and source line resistances in magnetoresistive random access memory

Program and erase methods and structures for byte-alterable flash memory

Non-volatile memory device with a programming current control scheme

Sub-1V bandgap reference circuit

Semiconductor device with split gate memory cell and fabrication method thereof

High voltage CMOS switch with reduced high voltage junction stresses

Two-transistor flash cell for large endurance application

Method of marginal erasure for the testing of flash memories

High voltage discharge circuit

Reference cell circuit for split gate flash memory

Circuit and programming method for the operation of flash memories to prevent programming disturbances

Circuit for programming a programmable memory cell

Nonvolatile semiconductor memory array with byte-program, byte-erase, and byte-read capabilities

Write buffer for resistive random access memory

CHIH YUE-DER

Reference cell configuration for sensing resistance states of MRAM bit cells

Structure and method for forming conductive path in resistive random-access memory device

Adjusting reference resistances in determining MRAM resistance states

YU HUNG-CHANG

Charge pump control scheme using frequency modulation for memory word line

Charge pump control scheme for memory word line

LIN KAI-CHUN

Differential MRAM structure with relatively reversed magnetic tunnel junction elements enabling writing using same polarity current

Read architecture for MRAM

CHEN HSU-SHUN

Power switch and operation method thereof

TAIWAN SEMICONDCUTOR MFG COMPA

Logic compatible arrays and operations

TAIWAN SEMICONDUCTOR MFG CO IN

Reference current generator with small temperature dependence

YANG TIEN-CHUN

Sensing circuit, memory device and data detecting method

HSIEH CHIA-TA

Structure and inhibited operation of flash memory with split gate

LEE JAM-WEM

Diode formed of PMOSFET and schottky diodes