Inventor
NUBER PAUL D
US8 patents
Patents
8 patentsUS6405358B1Jun 11, 2002
Method for estimating and displaying wiring congestion
AGILENT TECHNOLOGIES INC131 citations95
US6614260B1Sep 2, 2003
System and method for dynamic modification of integrated circuit functionality
AGILENT TECHNOLOGIES INC68 citations94
US6181182B1Jan 30, 2001
Circuit and method for a high gain, low input capacitance clock buffer
AGILENT TECHNOLOGIES INC12 citations70
US6775116B2Aug 10, 2004
Method and apparatus for preventing buffers from being damaged by electrical charges collected on lines connected to the buffers
AGILENT TECHNOLOGIES INC2 citations61
US6653858B2Nov 25, 2003
Bypass capacitance localization
AGILENT TECHNOLOGIES INC3 citations60
US6118169ASep 12, 2000
Method for increasing power supply bypassing while decreasing chip layer density variations
AGILENT TECHNOLOGIES INC2 citations58
US6734473B1May 11, 2004
Method of integrated circuit construction with port alignment and timing signal buffering within a common area
AGILENT TECHNOLOGIES INC1 citations50
US6894535B2May 17, 2005
Method and apparatus for ensuring signal integrity in a latch array
AGILENT TECHNOLOGIES INC0 citations48