Inventor

DUSANAPUDI MANOJ

IN68 patents

⚠️ This page may combine multiple inventors who share the name “DUSANAPUDI MANOJ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DUSANAPUDI MANOJ

IBM

Efficient validation/verification of coherency and snoop filtering mechanisms in computing systems

Identifying stale entries in address translation cache

System and method for using resource pools and instruction pools for processor design verification and validation

System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation

System and method for re-shuffling test case instruction orders for processor design verification and validation

Replicating test case data into a cache with non-naturally aligned data boundaries

Efficient testing of direct memory address translation

Efficient testing of direct memory address translation

Test case generation

Test case generation

System and method for testing SLB and TLB cells during processor design verification and validation

System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation

System and method for verification of cache snoop logic and coherency between instruction &amp; data caches for processor design verification and validation

System and method for testing a large memory area during processor design verification and validation

Replicating test code and test data into a cache with non-naturally aligned data boundaries

Synchronization of hardware agents in a computer system

Test case generation

Test case generation

System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validation

System and method for pseudo-random test pattern memory allocation for processor design verification and validation

Testing a non-core MMU

System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation

Testing speculative instruction execution with test cases placed in memory segments with non-naturally aligned data boundaries

Memory data management

Hazard generating for speculative cores in a microprocessor

Validation of store coherence relative to page translation invalidation

Validation of store coherence relative to page translation invalidation

List insertion in test segments with non-naturally aligned data boundaries

Method, system, and apparatus for stress testing memory translation tables

Method, system, and apparatus for stress testing memory translation tables

Identifying stale entries in address translation cache

Light weight and high throughput test case generation methodology for testing cache/TLB intervention and diagnostics

Test case generation for a hardware state space

System and method for testing multiple processor modes for processor design verification and validation

Efficiently generating effective address translations for memory management test cases

Stress testing a processor memory with a link stack

Replicating test case data into a cache with non-naturally aligned data boundaries

Efficiently generating effective address translations for memory management test cases

Identifying stale entries in address translation cache

Stress testing a processor memory with a link stack

Efficient validation/verification of coherency and snoop filtering mechanisms in computing systems

Efficient validation of transactional memory in a computer processor

Replicating test case data into a cache with non-naturally aligned data boundaries

Replicating test case data into a cache with non-naturally aligned data boundaries

GLOBALFOUNDRIES INC

Verification of dynamic logical partitioning

Verification of dynamic logical partitioning

Efficient validation of coherency between processor cores and accelerators in computer systems

DUSANAPUDI MANOJ

Hardware verification using acceleration platform

CHOUDHURY SHUBHODEEP ROY

System and method for generating fast instruction and data interrupts for processor design verification and validation

ARORA SAMPAN

Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode

System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation