Inventor

SEE ALEX

SG81 patents

⚠️ This page may combine multiple inventors who share the name “SEE ALEX”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SEE ALEX

CHARTERED SEMICONDUCTOR MFG

Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer

Method of forming contact to polysilicon gate for MOS devices

Method for fabricating an air gap shallow trench isolation (STI) structure

Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures

Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant

Method of multiple pulse laser annealing to activate ultra-shallow junctions

Activating source and drain junctions and extensions using a single laser anneal

Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process

Method to form high performance copper damascene interconnects by de-coupling via and metal line filling

Structure and method of liner air gap formation

Formation of silicided shallow junctions using implant through metal technology and laser annealing process

Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance

Method to fabricate RF inductors with minimum area

Versatile copper-wiring layout design with low-k dielectric integration

Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique

Method to form transistors and local interconnects using a silicon nitride dummy gate technique

Method to form MOS transistors with shallow junctions using laser annealing

Method to form MOS transistors with a common shallow trench isolation and interlevel dielectric gap fill

Parallel spiral stacked inductor on semiconductor material

Shallow trench isolation elevation uniformity via insertion of a polysilicon etch layer

Process flow for a performance enhanced MOSFET with self-aligned, recessed channel

Method for fabricating complementary silicon on insulator devices using wafer bonding

Method for buffer STI scheme with a hard mask layer as an oxidation barrier

Combined copper plating method to improve gap fill

Method of fabricating self-aligned metal barriers by atomic layer deposition on the copper layer

Method for pre-STI-CMP planarization using poly-si thermal oxidation

Method and apparatus for performing nickel salicidation

Method and apparatus for performing nickel salicidation

Dual silicon-on-insulator device wafer die

Method of fabricating a MOSFET device using a spike rapid thermal oxidation procedure

Simplified method to reduce or eliminate STI oxide divots

Method to form shallow trench isolations

Effective isolation with high aspect ratio shallow trench isolation and oxygen or field implant

Method of forming a high K metallic dielectric layer

Method for fabricating a small dimensional gate with elevated source/drain structures

Method of forming of high K metallic dielectric layer

Methods for eliminating metal corrosion by FSG

GLOBALFOUNDRIES SG PTE LTD

Small pitch and high density contact array

Through silicon vias

Grain boundary blocking for stress migration and electromigration improvement in CU interconnects

Planar passivation for pads

CMP head structure with retaining ring

CMP head structure

Integrated circuits with memory cells and methods of manufacturing the same

Integrated two-terminal device with logic device for embedded application

Integrated two-terminal device with logic device for embedded application

CHARTERED SEMICONDUCTORS MAUFA

Dual silicon-on-insulator device wafer die

UNIV SINGAPORE

Process flow for a performance enhanced MOSFET with self-aligned, recessed channel

CHARTERED SEMICONDUCTORS MANUF

Method for forming a region of low dielectric constant nanoporous material using a microemulsion technique

CHARTERED SEMICONDUCTOR MANFAC

Integrated circuit with self-aligned line and via and manufacturing method therefor