Inventor

KALTALIOGLU ERDEM

US75 patents

⚠️ This page may combine multiple inventors who share the name “KALTALIOGLU ERDEM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KALTALIOGLU ERDEM

INFINEON TECHNOLOGIES AG

Methods of forming MIM capacitors

FBEOL process for Cu metallizations free from Al-wirebond pads

Crack stop trenches

Barbed vias for electrical and mechanical connection between conductive layers in semiconductor devices

Capacitor integrated in a structure surrounding a die

Support structures for semiconductor devices

Polishing methods and apparatus

Back end interconnect with a shaped interface

Reduction of the shear stress in copper via&#39;s in organic interlayer dielectric material

Bilayer HDP CVD/PE CVD cap in advance BEOL interconnect structures and method thereof

Robust via structure and method

Crack stops for semiconductor devices

Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof

Via density rules

Capacitor and method of manufacturing a capacitor

Methods of manufacturing semiconductor devices and structures thereof

Passivated copper chip pads

MIM capacitors with catalytic activation layer

MIM capacitor with a cap layer over the conductive plates

Memory card with connecting portions for connection to an adapter

IBM

Bilayered metal hardmasks for use in Dual Damascene etch schemes

On-chip decoupling capacitor with bottom hardmask

E-fuse with hybrid metallization

Electronic fuse having a damaged region

Method of forming electronic fuse line with modified cap

Bilayered metal hardmasks for use in dual damascene etch schemes

TSV deep trench capacitor and anti-fuse structure

Selective local metal cap layer formation for improved electromigration behavior

Semiconductor article having a zig-zag guard ring and method of forming the same

Interconnect with hybrid metallization

Dual damascene structure and method

Method of forming an on-chip decoupling capacitor with bottom hardmask

Dual damascene structure and method

Random local metal cap layer formation for improved integrated circuit reliability

GLOBALFOUNDRIES INC

Interconnect structures with variable dopant levels

Interconnect structure having power rail structure and related method

Mechanically anchored backside C4 pad

IC structure with interdigitated conductive elements between metal guard structures

IC structure integrity sensor having interdigitated conductive elements

Interconnect structures for a security application

KALTALIOGLU ERDEM

Crack sensors for semiconductor devices

Crack sensors for semiconductor devices

Crack stop trenches

Crack stops for semiconductor devices

Pads with different width in a scribe line region and method for manufacturing these pads

RIESS PHILIPP

Dual damascene process

INFINEON TECHNOLOGIES CORP

Dual hardmask single damascene integration scheme in an organic low k ILD

KIM SUNOO

Through level vias and methods of formation thereof

BECK MICHAEL

Methods of manufacturing semiconductor devices and structures thereof

BARTH HANS-JOACHIM

Semiconductor devices and methods of manufacture thereof

Reduction of the shear stress in copper via's in organic interlayer dielectric material