Inventor

SKORDAS SPYRIDON

US51 patents

⚠️ This page may combine multiple inventors who share the name “SKORDAS SPYRIDON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SKORDAS SPYRIDON

IBM

Caller identity verification based on unique multi-device signatures

Substrate bonding with diffusion barrier structures

Wafer bonding misalignment reduction

Liquid cooling of semiconductor chips utilizing small scale structures

Reducing wafer bonding misalignment by varying thermal treatment prior to bonding

Wafer-to-wafer oxide fusion bonding

Gas-controlled bonding platform for edge defect reduction during wafer bonding

Gas-controlled bonding platform for edge defect reduction during wafer bonding

Advanced chip to wafer stacking

Advanced chip to wafer stacking

Wafer to wafer alignment

Semiconductor device including built-in crack-arresting film structure

Low-loss large-grain optical waveguide for interconnecting components integrated on a glass substrate

Distorting donor wafer to corresponding distortion of host wafer

Paint on micro chip touch screens

Paint on micro chip touch screens

Gas-controlled bonding platform for edge defect reduction during wafer bonding

Combination of TSV and back side wiring in 3D integration

Combination of TSV and back side wiring in 3D integration

Advanced chip to wafer stacking

Wafer to wafer alignment by LED/LSD devices

Process of monitoring dispensing of process fluids in precision processing operations

Cu—Cu bonding for interconnects on bridge chip attached to chips and packaging substrate

Paint on micro chip touch screens

Oxide-bonded wafer pair separation using laser debonding

Resist patterned redistribution wiring on copper polyimide via layer

Granting requests for authorization using data of devices associated with requestors

Semiconductor device including built-in crack-arresting film structure

Semiconductor device including built-in crack-arresting film structure

Edge trim processes and resultant structures

Semiconductor device including built-in crack-arresting film structure

Low-loss large-grain optical waveguide for interconnecting components integrated on a glass substrate

Semiconductor package with structures for cooling fluid retention

Manganese oxide hard mask for etching dielectric materials

Reducing wafer bonding misalignment by varying thermal treatment prior to bonding

Manganese oxide hard mask for etching dielectric materials

Facilitating chip dicing for metal-metal bonding and hybrid wafer bonding

Gas-controlled bonding platform for edge defect reduction during wafer bonding

Cognitive system for automatic risk assessment, solution identification, and action enablement

Selective etching of silicon wafer

Selective etching of silicon wafer

Strain detection structures for bonded wafers and chips

Handler wafer removal facilitated by the addition of an amorphous carbon layer on the handler wafer

GLOBALFOUNDRIES INC

Substrate bonding with diffusion barrier structures

Method to achieve ultra-high chip-to-chip alignment accuracy for wafer-to-wafer bonding process

Handler wafer removal by use of sacrificial inert layer

Wafer bonding using boron and nitrogen based bonding stack

FAROOQ MUKTA G

Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last

Via structure for three-dimensional circuit integration

LA TULIPE JR DOUGLAS C

Edge protection of bonded wafers during wafer thinning