Inventor
WINSTEL KEVIN R
US27 patents
⚠️ This page may combine multiple inventors who share the name “WINSTEL KEVIN R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
20 patentsUS9064937B2Jun 23, 2015
Substrate bonding with diffusion barrier structures
IBM29 citations94
US7888723B2Feb 15, 2011
Deep trench capacitor in a SOI substrate having a laterally protruding buried strap
IBM17 citations92
US7575970B2Aug 18, 2009
Deep trench capacitor through SOI substrate and methods of forming
IBM20 citations92
US8900885B1Dec 2, 2014
Wafer bonding misalignment reduction
IBM22 citations91
US9059039B2Jun 16, 2015
Reducing wafer bonding misalignment by varying thermal treatment prior to bonding
IBM6 citations84
US9536853B2Jan 3, 2017
Semiconductor device including built-in crack-arresting film structure
IBM3 citations73
US9543229B2Jan 10, 2017
Combination of TSV and back side wiring in 3D integration
IBM2 citations72
US9536809B2Jan 3, 2017
Combination of TSV and back side wiring in 3D integration
IBM3 citations72
US10615139B2Apr 7, 2020
Semiconductor device including built-in crack-arresting film structure
IBM0 citations52
US10211178B2Feb 19, 2019
Semiconductor device including built-in crack-arresting film structure
IBM0 citations52
US10134577B2Nov 20, 2018
Edge trim processes and resultant structures
IBM0 citations52
US10020279B2Jul 10, 2018
Semiconductor device including built-in crack-arresting film structure
IBM0 citations52
US9190303B2Nov 17, 2015
Reducing wafer bonding misalignment by varying thermal treatment prior to bonding
IBM0 citations52
US9059333B1Jun 16, 2015
Facilitating chip dicing for metal-metal bonding and hybrid wafer bonding
IBM1 citations52
US8372725B2Feb 12, 2013
Structures and methods of forming pre fabricated deep trench capacitors for SOI substrates
IBM0 citations52
US6353246B1Mar 5, 2002
Semiconductor device including dislocation in merged SOI/DRAM chips
IBM0 citations52
US9378966B2Jun 28, 2016
Selective etching of silicon wafer
IBM1 citations48
US9553054B2Jan 24, 2017
Strain detection structures for bonded wafers and chips
IBM0 citations42
US9171749B2Oct 27, 2015
Handler wafer removal facilitated by the addition of an amorphous carbon layer on the handler wafer
IBM0 citations42
US7560387B2Jul 14, 2009
Opening hard mask and SOI substrate in single process chamber
IBM0 citations42
FAROOQ MUKTA G
3 patentsUS8563403B1Oct 22, 2013
Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last
FAROOQ MUKTA G184 citations99
US8546961B2Oct 1, 2013
Alignment marks to enable 3D integration
FAROOQ MUKTA G9 citations84
US9214435B2Dec 15, 2015
Via structure for three-dimensional circuit integration
FAROOQ MUKTA G5 citations73