Inventor

XU YIHENG

US50 patents

⚠️ This page may combine multiple inventors who share the name “XU YIHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

XU YIHENG

IBM

Graphene sacrificial deposition layer on beol copper liner-seed for mitigating queue-time issues between liner and plating step

Self-aligned three dimensional chip stack and method for making the same

Self-aligned three dimensional chip stack and method for making the same

Structure and process for overturned thin film device with self-aligned gate and S/D contacts

Integrated circuit barrierless microfluidic channel

Multilayer structure in an integrated circuit for damage prevention and detection and methods of creating the same

Interconnect structure having large self-aligned vias

Structure and process for overturned thin film device with self-aligned gate and S/D contacts

Interconnect structures comprising capping layers with low dielectric constants and methods of making the same

Overturned thin film device with self-aligned gate and source/drain (S/D) contacts

Self-aligned three dimensional chip stack and method for making the same

Self-aligned three dimensional chip stack and method for making the same

Integrated circuit barrierless microfluidic channel

Integrated circuit barrierless microfluidic channel

Method for controlling the profile of an etched metallic layer

Method for controlling the profile of an etched metallic layer

Patterning through imprinting

Technique for fabrication of microelectronic capacitors and resistors

Semiconductor device processing with reduced wiring puddle formation

Real time alarm classification and method of use

ST MICROELECTRONICS INC

Recessed gate field effect transistor

Multilayer structure in an integrated circuit for damage prevention and detection and methods of creating the same

Modular fuses and antifuses for integrated circuits

Through silicon via structure for internal chip cooling

Interconnect structure having large self-aligned vias

Vertical gate all-around transistor

System and method of combining damascenes and subtract metal etch for advanced back end of line interconnections

Trench interconnect having reduced fringe capacitance

Technique for fabrication of microelectronic capacitors and resistors

Encapsulated metal interconnect

Electrostatic discharge devices for integrated circuits

Advanced interconnect with air gap

Modular fuses and antifuses for integrated circuits

Interconnect structure having large self-aligned vias

Structure and method for interconnect spatial frequency doubling using selective ridges

Encapsulated damascene interconnect structure for integrated circuits

Trench structure for high performance interconnection lines of different resistivity and method of making same

GLOBALFOUNDRIES INC

Silicon liner for STI CMP stop in FinFET

Gate oxide formation through hybrid methods of thermal and deposition processes and method for producing the same

Microwave annealing of flowable oxides with trap layers

Fin structures

Methods to form conductive thin film structures

Fin reveal forming STI regions having convex shape between fins

ZHANG JOHN H

Using backside passive elements for multilevel 3D wafers alignment applications

System and method of plating conductive gate contacts on metal gates for self-aligned contact interconnections

Recessed gate field effect transistor

HEFECHIP CORPORATION LTD

Methods for fabricating MRAM with void free interlayer dielectric

Methods for fabricating magnetoresistive random access memory with via under MJT

DYER THOMAS W

Structure and method for detecting defects in BEOL processing

LI WAI-KIN

Integration process to improve focus leveling within a lot process variation