Inventor

STANDAERT THEODORUS EDUARDUS

US28 patents

⚠️ This page may combine multiple inventors who share the name “STANDAERT THEODORUS EDUARDUS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STANDAERT THEODORUS EDUARDUS

IBM

Structure and method to improve FAV RIE process margin and electromigration

FinFET with dielectric isolation by silicon-on-nothing and method of fabrication

FinFET with dielectric isolation by silicon-on-nothing and method of fabrication

Dummy fin formation by gas cluster ion beam

Self-aligned dielectric isolation for FinFET devices

Structure and method for improved stabilization of cobalt cap and/or cobalt liner in interconnects

Semiconductor structure with deep trench thermal conduction

Interconnect structure and process of making the same

Method and structure to reduce the electric field in semiconductor wiring interconnects

Method and structure for finFET with finely controlled device width

Reliability of wide interconnects

CMOS devices with different metals in gate electrodes using spin on low-k material as hard mask

Structure and method for improved stabilization of cobalt cap and/or cobalt liner in interconnects

Semiconductor structure with deep trench thermal conduction

Semiconductor structure with deep trench thermal conduction

Replacement metal gate transistors using bi-layer hardmask

GLOBALFOUNDRIES INC

Dummy fin formation by gas cluster ion beam

FinFET with dielectric isolation by silicon-on-nothing and method of fabrication

Self-aligned dielectric isolation for FinFET devices

STANDAERT THEODORUS EDUARDUS

FinFET diode with increased junction area

FinFET with improved gate planarity

TESSERA LLC

Structure and method to improve FAV RIE process margin and Electromigration

Structure and method to improve FAV RIE process margin and electromigration

TESSERA INC

Structure and method to improve FAV RIE process margin and Electromigration

Structure and method to improve FAV RIE process margin and electromigration

HUANG ELBERT EMIN

Method and structure to reduce the electric field in semiconductor wiring interconnects

BONILLA GRISELDA

Capping of copper interconnect lines in integrated circuit devices

FALTERMEIER JONATHAN E

FinFET trench circuit