Inventor

FAN SU CHEN

US124 patents

⚠️ This page may combine multiple inventors who share the name “FAN SU CHEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FAN SU CHEN

IBM

Gate tie-down enablement with inner spacer

Embedded bottom metal contact formed by a self-aligned contact process for vertical transistors

Three-dimensional field effect device

Reflow interconnect using Ru

Gate tie-down enablement with inner spacer

Stable multiple threshold voltage devices on replacement metal gate CMOS devices

Interconnect structure including middle of line (MOL) metal layer local interconnect on etch stop layer

Contact area structure and method for manufacturing the same

Local interconnect structure including non-eroded contact via trenches

Integrated multiple gate length semiconductor device including self-aligned contacts

Borderless contact for ultra-thin body devices

Contacts and liners having multi-segmented protective caps

Transistor boundary protection using reversible crosslinking reflow

Reversible resistive memory logic gate device

Three-dimensional field effect device

Self-aligned contacts for MOL

Barrier-free vertical interconnect structure

Silicide formation for source/drain contact in a vertical transport field-effect transistor

Gate contact over active enabled by alternative spacer scheme and claw-shaped cap

Gate tie-down enablement with inner spacer

Gate contact over active region with self-aligned source/drain contact

Bottom contact formation for vertical transistor devices

Stack viabar structures

Three-dimensional field effect device

Embedded bottom metal contact formed by a self-aligned contact process for vertical transistors

Embedded bottom metal contact formed by a self-aligned contact process for vertical transistors

Forming self-aligned contact with spacer first

Stable multiple threshold voltage devices on replacement metal gate CMOS devices

Interconnect structure including middle of line (MOL) metal layer local interconnect on ETCH stop layer

STI region for small fin pitch in FinFET devices

Freestanding spacer having sub-lithographic lateral dimension and method of forming same

Middle-of-line interconnect having low metal-to-metal interface resistance

Stacked field effect transistor contacts

Bottom contact with self-aligned spacer for stacked semiconductor devices

GLOBALFOUNDRIES INC

Methods of forming replacement gate structures for transistors and the resulting devices

Self-aligned gate tie-down contacts with selective etch stop liner

Methods of forming a combined gate and source/drain contact structure and the resulting device

Method for single fin cuts using selective ion implants

Vertical field effect transistor with self-aligned contacts

Method of forming vertical FinFET device having self-aligned contacts

TAIWAN SEMICONDUCTOR MFG

Three dimensional IC device and alignment methods of IC device substrates

Interconnect structure and method of fabricating same

Pre-treatment for salicide process

Wiring structure to minimize stress induced void formation

XIE RUILONG

Formation of the dielectric cap layer for a replacement gate structure

Method for forming a self-aligned contact opening by a lateral etch

Recessing and capping of gate structures with varying metal compositions

HORAK DAVID V

Method of forming replacement metal gate with borderless contact and structure thereof

KOBURGER III CHARLES W

Method of forming self-aligned local interconnect and structure formed thereby

GLOBALFOUNFRIES SINGAPORE PTE LTD

Formation of the dielectric cap layer for a replacement gate structure