Inventor

LABONTE ANDRE P

US30 patents

⚠️ This page may combine multiple inventors who share the name “LABONTE ANDRE P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LABONTE ANDRE P

IBM

Gate tie-down enablement with inner spacer

Gate tie-down enablement with inner spacer

Local interconnect structure including non-eroded contact via trenches

Gate tie-down enablement with inner spacer

Sacrificial gate spacer regions for gate contacts formed over the active region of a transistor

Gate tie-down enablement with inner spacer

Gate tie-down enablement with inner spacer

Local interconnect structure including non-eroded contact via trenches

Gate tie-down enablement with inner spacer

Gate tie-down enablement with inner spacer

Gate tie-down enablement with inner spacer

Gate tie-down enablement with inner spacer

Gate tie-down enablement with inner spacer

GLOBALFOUNDRIES INC

Methods of forming a gate contact for a transistor above an active region and the resulting device

Self-aligned gate contact formation

Contact structures

Methods of forming a semiconductor device with a gate contact positioned above the active region

Interconnect structure having reduced resistance variation and method of forming same

NAT SEMICONDUCTOR CORP

Apparatus and method for isolating integrated circuit components using deep trench isolation and shallow trench isolation

Semiconductor device having localized insulated block in bulk substrate and related method

System and method for providing a single deposition emitter/base in a bipolar junction transistor

System and method for controlling an etch process for a single crystal having a buried layer

APPLIED MATERIALS INC

Methods of forming variable-depth device structures

Method for manufacturing optical device structures

Method for manufacturing optical device structures

Method for manufacturing optical device structures

LABONTE ANDRE P

Alignment tolerant semiconductor contact and method

Integrated circuit contact structure and method

Non-volatile memory cell with asymmetrical split gate and related system and method

GLOBALFOUNDRIES US INC

Interconnect structures of semiconductor devices having a via structure through an upper conductive line