Inventor

MEHTA SANJAY C

US92 patents

⚠️ This page may combine multiple inventors who share the name “MEHTA SANJAY C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MEHTA SANJAY C

IBM

Air gap spacer formation for nano-scale semiconductor devices

Air gap spacer formation for nano-scale semiconductor devices

Gate tie-down enablement with inner spacer

Bottom spacer formation for vertical transistor

Self aligned top extension formation for vertical transistors

Pure boron for silicide contact

Structure and method of chemically formed anchored metallic vias

Reliable BEOL integration process with direct CMP of porous SiCOH dielectric

Protection of high-K dielectric during reliability anneal on nanosheet structures

Air gap spacer formation for nano-scale semiconductor devices

Self aligned top extension formation for vertical transistors

Bottom spacer formation for vertical transistor

Method of forming vertical transistor having dual bottom spacers

Fabrication of vertical doped fins for complementary metal oxide semiconductor field effect transistors

Vertical transistor bottom spacer formation

Gate tie-down enablement with inner spacer

POC process flow for conformal recess fill

Solid state diffusion doping for bulk finFET devices

POC process flow for conformal recess fill

Pure boron for silicide contact

Replacement metal gate FinFET

Field effect transistor device spacers

POC process flow for conformal recess fill

Spacer replacement for replacement metal gate semiconductor devices

Replacement metal gate FinFET

Replacement metal gate FinFET

Hardmask for reliability of silicon based dielectrics

Method of fabricating a wire bond pad with Ni/Au metallization

Spacer formation on semiconductor device

Phase change memory cell with a wrap around and ring type of electrode contact and a projection liner

Approach to bottom dielectric isolation for vertical transport fin field effect transistors

Gate first technique in vertical transport FET using doped silicon gates with silicide

Gate tie-down enablement with inner spacer

Approach to bottom dielectric isolation for vertical transport fin field effect transistors

Selective contact etch for unmerged epitaxial source/drain regions

Protection of high-K dielectric during reliability anneal on nanosheet structures

Approach to bottom dielectric isolation for vertical transport fin field effect transistors

Vertical transistor top epitaxy source/drain and contact structure

Fabrication of vertical doped fins for complementary metal oxide semiconductor field effect transistors

Modulating transistor performance

High thermal budget compatible punch through stop integration using doped glass

Effective device formation for advanced technology nodes with aggressive fin-pitch scaling

Hydrogen-free silicon-based deposited dielectric films for nano device fabrication

High thermal budget compatible punch through stop integration using doped glass

High thermal budget compatible punch through stop integration using doped glass

Gate tie-down enablement with inner spacer

BERLINER NATHANIEL C

Method to enable compressively strained pFET channel in a FinFET structure by implant and thermal diffusion

TESSERA LLC

Air gap spacer formation for nano-scale semiconductor devices

ST MICROELECTRONICS INC

Method to enhance strain in fully isolated finFET structures

GLOBALFOUNDRIES INC

Wafer bonding using boron and nitrogen based bonding stack