Inventor

NAKAMICHI MASARU

JP20 patents

⚠️ This page may combine multiple inventors who share the name “NAKAMICHI MASARU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NAKAMICHI MASARU

RENESAS ELECTRONICS CORP

Semiconductor integrated circuit device with reduced leakage current

Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device

Semiconductor integrated circuit device with reduced leakage current

Semiconductor integrated circuit device with reduced leakage current

Semiconductor integrated circuit device with reduced leakage current

RENESAS TECH CORP

Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device

Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device

Semiconductor integrated circuit device with reduced leakage current

Semiconductor integrated circuit device with reduced leakage current

HITACHI ULSI SYS CO LTD

Semiconductor integrated circuit device with reduced leakage current

Semiconductor integrated circuit device with reduced leakage current

Semiconductor integrated circuit device with reduced leakage current

Semiconductor integrated circuit device

OSADA KENICHI

Semiconductor integrated circuit device with reduced leakage current

Semiconductor integrated circuit device with reduced leakage current

Semiconductor integrated circuit device with reduced leakage current

NATIONAL INSTITUTES FOR QUANTUM SCIENCE AND TECH

Beryllium solution production method, beryllium production method, beryllium hydroxide production method, beryllium oxide production method, solution production device, beryllium production system, and beryllium

Method for producing beryllium solution, method for producing beryllium, method for producing beryllium hydroxide, method for producing beryllium oxide, and beryllium oxide

MACRONIX INT CO LTD

Memory device with multi-layered charge storage stack

SAKAI TAKESHI

Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device